Semiconductor device having vertical mosfet with superstructure structure and manufacturing method thereof

Abstract

The present invention provides a semiconductor device having a vertical MOSFET with a superstructure structure and a method of manufacturing the same. The method of manufacturing a semiconductor device comprises preparing a semiconductor substrate (10) having a first semiconductor layer (12) formed on a substrate (11), forming a first recess (12a) on the first semiconductor layer, and forming a first recess (12a) in the first recess. A plurality of grooves (15) are formed on the above-mentioned first semiconductor layer, and the second semiconductor layer (16) buried in the above-mentioned grooves and in the above-mentioned first recess is epitaxially grown to form a The SJ structure of the PN column formed by the above-mentioned first semiconductor layer between the above-mentioned second semiconductor layer and the plurality of trenches, forming a channel layer (17) and a source region (18) connected to the channel layer on the above-mentioned SJ structure , forming a gate electrode (23) via a gate insulating film (22) on the above-mentioned channel layer, and forming a source electrode (25) connected to the above-mentioned source region, and forming a drain electrode (26) on the back surface of the above-mentioned substrate , thus forming a vertical MOSFET.

Description

[0001] This application is based on Japanese application No. 2012-268412 filed on December 7, 2012, Japanese application No. 2012-268413 filed on December 7, 2012, and Japanese application No. 2013-222256 filed on October 25, 2013 No., and the contents described in these applications are referred to in the present application. technical field [0002] The present invention relates to a semiconductor device having a vertical MOSFET having a superjunction (hereinafter referred to as SJ) structure formed by epitaxially growing a second semiconductor layer in a trench formed in a first semiconductor layer, and a method for manufacturing the same. SJ construction. Background technique [0003] Conventionally, there is known a semiconductor device having an SJ structure in which n-type columns and p-type columns are alternately and repeatedly formed (for example, refer to Patent Document 1). When manufacturing a semiconductor device with an SJ structure, for example Figure 9 As ...

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Problems solved by technology

[0005] However, when making p - p - Type layer J5 and n - The flattening and polishing of the surface of the pattern layer J2 has a large variation, and the depth of the PN column varies, and the desired depth cannot be obtained with high precision.

The reason is that, although there is also the problem of the precision of the epitaxial growth itself, to a greater extent, p - Type layer J5 and n - The planarization polishing of the type layer J2 becomes the polishing process of the same semiconductor material (such as silicon), and it is difficult to stop polishing at the desired film thickness in principle.

In addition, when the depth of the PN column varies in this way, the withstand voltage of the semiconductor device varies and the device characteristics deteriorate.

[0006] In addition, there is also the problem of using p on the SJ structure after forming the SJ structure - Type layer J6 grows epitaxially, but due to the surface of the SJ structure and the p - The inter-constructive handling of type layer J6, while the upper side of the p - Abnormal growth of type layer J6 degrades device characteristics

[0007] Furthermore, since independently performing p - The formation process of the type layer J6, so there are also problems such as increased manufacturing steps and higher manufacturing costs.

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