Storage method and system based on stored data anti-jamming of ERC32 processor

Abstract

The invention provides a storage method and system based on stored data anti-jamming of an ERC32 processor. The abnormal trap mechanism of an ERC32 processor is utilized, the EDAC method and the triple-modular redundancy method are combined, and an internal memory is periodically refreshed by software. If one-bit turnover occurs, the EDAC method is adopted for error correction; if multi-bit errors occur, wrong data in units are eliminated at first, a specific abnormality is triggered to reset, and data recovery is realized through three-out-of-two principle. All data on the bottom program follow the three-out-of-three principle, and independent three-out-of-two principle of the upper-layer application program before use of each data is not required, so that the software complexity is reduced and the software reliability is improved.

Description

technical field [0001] The invention relates to reliability design of data transmission of satellite on-board equipment, in particular to an anti-interference storage method and system based on ERC32 processor memory data. Background technique [0002] The spaceborne computer is used in the outer space environment. Due to the lack of protection of the earth's magnetic field, the data bits in the memory unit are more likely to be affected by factors such as solar storms and cosmic rays. The transient "0" becomes "1" or "1" ” becomes a failure condition of “0”, this phenomenon is called “single event upset”. [0003] At present, there are two main methods for anti-jamming of memory data in satellite models: one method is to detect and correct errors in the hardware circuit EDAC, and the software regularly reads and writes and refreshes each unit in the memory. The code bit, combined with the EDAC algorithm, enables the read data to correct or detect possible bit flips; anothe...

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Problems solved by technology

[0004] The above two memory data anti-jamming methods have obvious deficiencies: EDAC error detection and correction method can only correct 1-bit error in each 32-bit unit due to the limitation of supervised code bit length, but cannot correct 2-bit and 2-bit errors. The data in the latter out of three is stored in three areas with far apart address intervals, and the possibility of being completely destroyed is very low, but the general data three-mode redundancy recovery will first read three If there is an error in the data of the memory unit, it will cause a trap in the fault trap (TRAP IN TRAP). This situation will cause the program to fall into an infinite loop. In addition, the overhead of memory occupied by triple-mode redundancy is relatively large, especially in a large number of software. When adopted, the implementation of coding will reduce the readability of the software and increase the complexity, which will affect the reliability of the software on the other side

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