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Pixel unit, preparation method thereof, array substrate and display device

A technology for pixel units and array substrates, applied in electrical components, semiconductor/solid-state device manufacturing, optics, etc., can solve the problems of limited space size of via holes, difficult to realize, reduce the slope of via holes, etc., and reduce the cracking of conductive materials risk effect

Inactive Publication Date: 2015-08-26
HEFEI BOE OPTOELECTRONIC TECH CO LTD +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In fact, due to the tight arrangement of pixel units and the limited space size of the via hole, it is difficult to realize the method of reducing the slope of the via hole.

Method used

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  • Pixel unit, preparation method thereof, array substrate and display device
  • Pixel unit, preparation method thereof, array substrate and display device
  • Pixel unit, preparation method thereof, array substrate and display device

Examples

Experimental program
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Effect test

no. 1 example

[0039] In this embodiment, a pixel unit is provided. Refer below image 3 The structure of the pixel unit of this embodiment will be described in detail. It should be clarified that the pixel unit defined in this embodiment does not include gate lines and data lines. The pixel unit can be used to form a common array substrate or a dual-gate array substrate after the gate lines and data lines are properly arranged.

[0040] image 3 It is a schematic structural diagram of a pixel unit according to the first embodiment of the present invention. Please refer to image 3 , the pixel unit in this embodiment includes: a thin film transistor 20 , a pixel electrode 41 and a common electrode 43 .

[0041] The thin film transistor 20 is a bottom gate field effect transistor, comprising: a gate 21, a gate insulating layer 22 formed above the gate 21, an active layer 23 formed above the gate insulating layer 22, and an active layer 23 formed on the active layer 23. source 24 and dra...

no. 3 example

[0089] In this embodiment, an array substrate is provided. Figure 5 It is a top view of the array substrate according to the third embodiment of the present invention. For the purpose of clearly describing this embodiment, the passivation layer and the common electrode above the pixel electrodes are omitted.

[0090] Please refer to Figure 5 , the array substrate includes: a glass substrate; gate lines 1 formed on the glass substrate; and data lines 2 formed on the glass substrate and substantially perpendicular to the gate lines 1 . Among them, several pixel regions are defined between the gate line 1 and the data line 2 . Each pixel area includes what is described in Embodiment 1, such as image 3 Pixel units shown.

[0091] In the pixel unit, the gate of the thin film transistor is connected to the gate line, and the source of the thin film transistor is connected to the data line.

[0092] As an array substrate in this embodiment, it may be the following array subst...

no. 5 example

[0097] In this embodiment, an array substrate is provided. The difference between the array substrate and the array substrate of the third embodiment is that it is an array substrate using OLED technology. Specifically, in the pixel unit, the common electrode and the pixel electrode are not separated by a passivation layer, but have an organic light-emitting layer. Under the condition that the common electrode and the pixel electrode provide voltage, the organic light-emitting layer can emit light with preset colors and gray scales. Regarding the content of the via hole, reference may be made to the content of the first embodiment; for the content of the organic light emitting layer, reference may be made to relevant documents in the prior art, and details will not be repeated here.

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Abstract

The invention provides a pixel unit, a preparation method thereof, an array substrate and a display device. The pixel unit comprises a thin film transistor, an insulating layer, a pixel electrode and a first heightening layer and / or a second heightening layer, wherein the insulating layer is formed on the thin film transistor, a preset position of the insulating layer forms a via hole so as to expose a drain electrode of the thin film transistor below; the pixel electrode is formed on the insulating layer and electrically connected with the drain electrode of the thin film transistor at the via hole; and the first heightening layer and / or the second heightening layer are / is formed below the via hole so as to heighten the via hole. According to the invention, the slope of the via hole is reduced through additionally arranging the heightening layers at the bottom part of the organic film via hole. Meanwhile, the heightening layers can be formed by a gate metal layer and / or an active layer which are / is not etched in the technological process, thereby not increasing any production cost or processing difficulty.

Description

technical field [0001] The invention relates to the field of liquid crystal display, in particular to a pixel unit, a preparation method thereof, an array substrate and a display device. Background technique [0002] The basic structure of a Thin Film Transistor Liquid Crystal Display (TFT LCD for short) includes: an array substrate and a counter substrate. Wherein, a liquid crystal layer is filled between the array substrate and the opposite substrate, and a liquid crystal cell (Cell) structure is formed through a cell alignment process. [0003] Several pixel units are distributed on the base substrate 10 of the array substrate. figure 1 It is a schematic cross-sectional view of a pixel unit on an array substrate in the prior art. Please refer to figure 1 , each pixel unit includes: a thin film transistor (TFT) 20 , a pixel electrode 41 and a common electrode 43 . [0004] The thin film transistor 20 includes: a gate 21, a gate insulating layer 22 formed above the gate...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L27/12H01L21/77G02F1/1362G02F1/1368
CPCG02F1/136227G02F1/1368H01L27/124H01L27/1259H01L29/41733H01L29/78606H01L27/1248H01L27/1244G02F1/13606H10K59/123H10K59/88H10K59/1213G02F1/133345G02F1/134309G02F1/13439G02F1/136286G02F2201/121G02F2201/123H01L27/1222H01L29/78618
Inventor 尹小斌陈传宝孙东领王立森
Owner HEFEI BOE OPTOELECTRONIC TECH CO LTD
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