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A semiconductor structure with vertical via interconnection and its manufacturing method

A vertical via hole and semiconductor technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, semiconductor/solid-state device components, etc., can solve problems such as difficult thermodynamic reliability problems, thermal expansion coefficient mismatch, and threats to thermodynamic reliability. Achieve the effect of improving thermodynamic reliability and improving thermal stress problems

Active Publication Date: 2017-12-08
PEKING UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Among them, the solid TSV interconnection technology solution is suitable for three-dimensional integration applications of small aperture and high-density TSV interconnection, such as 3D IC, but due to the thermal expansion coefficient mismatch of solid TSV interconnection materials, its thermodynamic reliability is a problem, especially when large When TSVs with apertures and high aspect ratios are interconnected, such as when applied to three-dimensionally integrated TSV adapter boards such as MEMS and micro-nano sensors, the problem of thermodynamic reliability is more difficult
Compared with the solid TSV interconnection, the ring-shaped TSV interconnection scheme filled with organic matter has made some progress in alleviating the problem of thermal stress, and has certain advantages in the application of TSV adapter boards with low-density I / O requirements. However, due to its circular cross-section Ring type, when its temperature changes, due to its symmetry, it will still form a radial extrusion or stretching effect on the surrounding substrate, which is still a major threat to its thermodynamic reliability.

Method used

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  • A semiconductor structure with vertical via interconnection and its manufacturing method
  • A semiconductor structure with vertical via interconnection and its manufacturing method
  • A semiconductor structure with vertical via interconnection and its manufacturing method

Examples

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Effect test

Embodiment 1

[0031] The semiconductor structure with through-silicon vias disclosed in this embodiment can refer to figure 1 , the semiconductor structure includes a substrate 100, a plurality of petal-shaped vertical via interconnections and a metal interconnection layer, wherein:

[0032] The substrate 100 is silicon or glass, having opposite first surface 000 and second surface 200;

[0033] The petal-shaped vertical through-hole interconnection consists of a vertical through-hole 101 embedded in the substrate with a petal-shaped cross-section vertically penetrating through the first surface 000 and the second surface 200 of the substrate, and A metal layer 102 conformally covering the sidewall of the vertical via hole;

[0034] There are metal interconnection layers on the first surface 000 and the second surface 200 of the substrate respectively, and the metal interconnection layers are respectively composed of conductive metal layers 001, 201 and dielectric layers 002, 202;

[0035...

Embodiment 2

[0039] This embodiment discloses a semiconductor structure manufacturing method with vertical via interconnection, which can be referred to figure 2 , combined below figure 2 To further describe the method:

[0040] Step 1, providing a substrate 100, the substrate is a silicon wafer or a glass wafer, the substrate 100 has an opposite first surface 000 and a second surface 200, and a plurality of flower petal cross-sections are fabricated in the substrate. Shaped shaped through hole 101, such as figure 2 As shown in (a); the cross-section of the special-shaped through hole 101 can be three or four petals, and has a convex free end. The special-shaped through hole 101 is made by deep reactive ion etching (DRIE), laser ablation, sandblasting, Ultrasonic processing, etc.;

[0041] If the substrate used is a silicon wafer, after making the special-shaped through hole 101, it also includes forming an insulating layer 103 on the side wall of the through hole. The insulating lay...

Embodiment 3

[0045] This embodiment discloses a semiconductor structure manufacturing method with vertical via interconnection, which can be referred to image 3 , which will be combined below image 3 To further explain this method:

[0046] In step 1, the substrate 100 has opposite first surface 000 and second surface 200, and a plurality of petal-shaped shaped blind holes 101 are fabricated in the substrate, such as image 3 As shown in (a); the cross-section of the special-shaped blind hole 101 can be three or four petals, with a convex free end, and the special-shaped through hole 101 is made by deep reactive ion etching (DRIE), laser ablation, sandblasting, Ultrasonic processing, etc.;

[0047] If the substrate used is a silicon wafer, after making the special-shaped through hole 101, it also includes forming an insulating layer 103 on the side wall of the through hole. The insulating layer 103 can have a one-layer or multi-layer structure, and its material is oxide Silicon, silic...

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PUM

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Abstract

The present invention provides a semiconductor structure with vertical via interconnection and a manufacturing method thereof. The semiconductor structure includes a substrate, at least one vertical via interconnection with a petal-shaped cross section, and a metal interconnection layer; the substrate has opposite first and second surfaces; the vertical via interconnection includes A petal-shaped vertical via hole vertically penetrating through the first surface and the second surface of the substrate, and a metal layer conformally covering the sidewall of the vertical via hole, and the petal-shaped vertical via hole has a protruding free end; the metal interconnection layer is disposed on the first surface and / or the second surface of the substrate. The invention can release the thermal stress caused by the thermal expansion coefficient mismatch through the protruding free end in the vertical through hole, can improve the thermal stress problem faced by the traditional solid or hollow silicon via interconnection structure, and improve the interconnection capacity of the vertical through hole. Thermodynamic reliability of semiconductor structures.

Description

technical field [0001] The invention relates to the field of semiconductor structure manufacturing, in particular to a semiconductor structure with vertical through-hole interconnection and a manufacturing method thereof. Background technique [0002] As Moore's Law approaches the physical limit, TSV three-dimensional packaging technology (Through-Si-Via, TSV) realizes three-dimensional integration at the chip level through TSV interconnection technology. It has the characteristics of small volume, high density and three-dimensional heterogeneous integration, and is considered by the industry. It is an important way to break through or even surpass Moore's Law, and has become the frontier and hot spot in the field of advanced packaging and even the field of microelectronics. [0003] TSV / TGV adapter plate technology (Through-Glass-Via, TGV) is an important development direction derived from TSV interconnection technology. The characteristics of small size, high density, and...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L23/528H01L21/768
Inventor 马盛林陈兢夏雁鸣官勇罗荣峰任奎丽
Owner PEKING UNIV
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