Self-aligned double patterning method and fin field effect transistor manufacturing method

Abstract

Provided are a self-aligned double patterning method and a fin field effect transistor manufacturing method. The self-aligned double patterning method comprises: providing a material layer to be etched; successively forming a first sacrificial layer and a photoresist pattern on the material layer to be etched; etching the first sacrificial layer by using the photoresist pattern as a mask in order to form a first sacrificial layer pattern; removing the photoresist pattern and forming a mask material layer covering the first sacrificial layer pattern on the material layer to be etched; forming a second sacrificial layer on the mask material layer; removing the second sacrificial layer and the mask material layer on the first sacrificial layer pattern; removing the rest second sacrificial layer; etching the rest mask material layer until the material layer to be etched is exposed; removing the first sacrificial layer pattern; and etching the material layer to be etched by using the rest mask material layer as a mask. The fin field effect transistor manufacturing method comprises the above self-aligned double patterning method. A symmetric mask with a rectangular cross section can be formed by using the methods.

Description

Technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a self-aligned dual patterning method and a method for manufacturing a fin field effect transistor. Background technique [0002] In the field of semiconductor manufacturing, photoresist materials are used to transfer mask patterns to one or more layers of materials, for example, to transfer mask patterns to metal layers, dielectric layers or semiconductor substrates. However, as the feature size of the semiconductor process continues to shrink, it becomes more and more difficult to form a mask pattern with a small feature size in the material layer using a photolithography process. [0003] In order to improve the integration of semiconductor devices, the industry has proposed a variety of double patterning processes. Among them, the self-aligned double patterning (SADP) process is one of them. Refer to Figure 1 to Figure 5 Shown. [0004] reference figure 1 As show...

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Problems solved by technology

[0009] However, after the sidewall 51 is formed by the above process, the cross section of the sidewall 51 is tapered and its shape is asymmetric, so that the material layer 20 to be etched is etched using the sidewall 51 as a mask. , it will affect the morphology of the final pattern to be etched 21, and eventually damage the electrical performance of the subsequently formed semiconductor device

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