Static Timing Analysis Method for Thermally Stressed Circuits Containing TSVs

Abstract

The invention belongs to a method for static timing analysis of thermal stress circuits containing through-silicon vias, which includes the following steps: (1) determining the type of through-silicon vias used in the circuit; The physical parameters of the transistor; (3) using the mathematical model of stress to obtain the radial stress and hoop stress of each layer material of a single TSV in the cylindrical coordinate system; (4) solving the boundary conditions of each coefficient in the stress expression; (5) Convert the stress in the cylindrical coordinate system to the stress in the Cartesian coordinate system; (6) Obtain the total thermal stress distribution caused by multiple TSVs according to the linear superposition criterion; (7) Calculate different channel directions (8) Add the change of carrier mobility to the gate-level netlist of the circuit, and run PrimeTime for static timing analysis under timing constraints to obtain the longest circuit Path delay and timing margin variation.

Description

technical field [0001] The invention belongs to the technical field of microelectronics, and in particular relates to a static timing analysis method for thermal stress circuits with through-silicon holes. Background technique [0002] When studying the thermomechanical reliability of TSV-based 3D integrated circuits, the key is the acquisition of thermal stress. The acquisition of thermal stress is obtained through finite element analysis software and mathematical modeling. Among them, the finite element analysis is solved by dividing the finite element model of the through-silicon via, and the solution speed is slow, especially in the large-scale three-dimensional integrated circuit design, the finite element model is very complicated, which consumes a lot of time and storage resources. The mathematical modeling of the thermal stress can quickly obtain the thermal stress of the through-silicon via, so that the thermal-mechanical reliability of the through-silicon via can ...

AI Technical Summary

Problems solved by technology

[0004] Krit Athikulwonge. Jae-Seok Yang. David Z Pan. Sung Kyu Lim. "Impact of Mechanical Stress on the Full Chip Timing for Through-Silicon-Via-based 3-DICs". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, VOL.32, NO.6, JUNE 2013, this paper discloses an analysis method that considers the influence of TSV thermal stress on the timing of 3D integrated circuits, but the stress model used in the article is simple uniaxial stress and does not consider other layer material, which will reduce the accuracy of thermal stress acquisition; and this method only considers cylindrical TSVs and does not consider other types of TSVs, so this method is not suitable for At the same time, the influence of the direction of the device channel is not taken into account, which will cause the accuracy of the carrier mobility change to decrease when the device channel in the circuit is along different crystal directions, so that Unreliable Timing Analysis Results for Circuits

Images