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A High-Level Synthetic Scheduling Method Based on Linear Delay Model

A high-level synthesis and scheduling method technology, applied in the field of hardware circuit structure design, can solve the problems of inability to meet the development needs of integrated circuit design, high algorithm time complexity, poor overall scheduling effect, etc., to reduce the algorithm time complexity, meet the Development requirements, effects of reduced accuracy

Active Publication Date: 2018-06-26
SYSU CMU SHUNDE INT JOINT RES INST +1
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  • Claims
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Problems solved by technology

However, in the current high-level scheduling method, the estimation method for the delay required by the data path either has a high algorithm time complexity or a low estimation accuracy, which makes the overall scheduling effect poor and cannot meet the development needs of integrated circuit design.

Method used

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  • A High-Level Synthetic Scheduling Method Based on Linear Delay Model
  • A High-Level Synthetic Scheduling Method Based on Linear Delay Model
  • A High-Level Synthetic Scheduling Method Based on Linear Delay Model

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Embodiment

[0047] First, the control data flow diagram is described, figure 1 It is a schematic diagram of the control data flow graph. The control data flow graph is the execution operation object of the scheduling algorithm. It is a directed graph that includes data operations, data dependencies, control jumps and other related information input into the circuit description of the system. The control data flow graph can be divided into two parts: nodes and edges, where nodes include operation nodes and basic blocks. An operation node refers to a set of operation operations appearing in the input circuit description, and according to different control relationships, one or more sets of operation nodes can constitute a basic block. In the figure, the solid line represents the data dependency edge, the dotted line represents the control dependency edge, each ellipse represents an operation node, and each box represents a basic block. Every circuit description can be represented by such a...

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Abstract

The invention discloses a high-level comprehensive dispatching method based on a linear delaying model. The high-level comprehensive dispatching method comprises: after acquiring input circuit description, constructing a control data flow diagram; clustering operation calculation in the control data flow diagram and establishing a corresponding delaying model for each type of operation calculation; carrying out delay estimation on the operation calculation based on the delaying model; calculating delaying information of any data path in the control data flow diagram; marking the calculated delaying information into the control data flow diagram, and constructing a dispatching diagram according to the control data flow diagram with the delaying information; and dispatching the dispatching diagram by adopting a difference constrained system dispatching algorithm to obtain a dispatching result. According to the high-level comprehensive dispatching method based on the linear delaying model, disclosed by the invention, the accuracy of the estimation is guaranteed by using the linear delaying model, and algorithm time complexity, namely polynomial time complexity, is reduced; a target function can be rapidly and accurately solved to obtain an accurate result, so that the whole dispatching result is more superior, and furthermore, a hardware circuit structure can be more rapidly and accurately generated.

Description

technical field [0001] The invention relates to the field of hardware circuit structure design, in particular to a high-level comprehensive scheduling method based on a linear delay model. Background technique [0002] Since the early 1960s, the development of microelectronics-related manufacturing process technology has followed the prediction made by Gordon Moore, the co-founder of Intel Corporation, that is, Moore's Law-every 1.5 years, the number of circuits integrated on an integrated circuit chip It will be doubled, and the overall performance of the microprocessor will also be doubled. The rapid development of integrated circuit products puts forward more stringent requirements for its design work, and also brings serious problems to the designer's design efficiency. Advances in design tools and design methods for integrated circuits have become an integral part of promoting the development of the integrated circuit industry. [0003] At present, the early design of...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F17/50
Inventor 郭建平王自鑫陈弟虎罗新潮黄侃涂玏
Owner SYSU CMU SHUNDE INT JOINT RES INST
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