Chip post-assembly active buried packaging structure and its production process

Abstract

The present invention relates to a chip back assembly active buried structure and a manufacturing process thereof. The manufacturing process comprises a step of providing a carrier plate for carrying a chip, a step of temporarily bonding a substrate dam body on the carrier plate through a damming dielectric layer, and arranging a groove body on the dam body, a step of mounting a chip in the groove body in a way that the front convex point of the chip is connected to the copper convex point of the upper surface of the carrier plate and the back side of the chip is exposed, a step of bonding the chip and the carrier plate through lamination and filling the damming dielectric layer at the bottom of the chip and the gap between the chip and the substrate dam body, and a step of planting a BGA ball on a carrier plate lower surface pad. By using the chip back buried process, combined with the high temperature lamination process, the bonding of the chip convex point and the carrier plate convex point is directly completed, the damming dielectric layer is arranged between the chip and the carrier plate, the process is simple, the substrate process compatibility is good, the process cost is greatly reduced and the chip package performance is improved greatly, the back side of the chip is exposed by using the chip back assembly mode, and the problem of difficult heat radiation of chip embedment is solved.

Description

technical field [0001] The invention relates to an active embedded packaging structure after chip assembly and a production process thereof, and belongs to the technical field of advanced microelectronic packaging. Background technique [0002] The active embedded package structure in the prior art mainly adopts the method of embedding in front of the chip, and the main problems of this method are low yield and poor heat dissipation of the chip. Specifically, CN103474361A discloses a packaging process and packaging structure of an embedded active embedded functional substrate. The packaging process includes: a surface-shaped secondary packaging component; Blind holes are opened on the two main surfaces corresponding to the bumps, and blind holes are drilled to the bumps; through holes are formed on the secondary packaging components, and the through holes pass through the secondary packaging components; The blind hole and the through hole are metallized as a seed layer, and...

AI Technical Summary

Problems solved by technology

However, after the chip is embedded in the substrate, the back of the chip needs to be metallized or non-metallized. For high-power devices, this form of packaging structure cannot completely solve the heat dissipation problem of the chip.

[0003] In addition, the currently used post-embedding method of chips is mainly through tin bump welding. During the welding process, flux for welding will be introduced, which will reduce the reliability of the entire package module, and also bring about process comparison. Complicated and other disadvantages

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