TMR-based implementation and fault injection simulation platform and simulation method

Abstract

A TMR-based implementation and fault injection simulation platform and simulation method take a TMR-injection system as a target authentication object and a basic function system as a simulation reference model and completes fault injection and simulation of a RTL level constrained by a fault injection constraint file. According to the simulation platform and simulation method provided by the present invention, a constraint by using a logic circuit is realized and a logic synthesis constraint condition is stipulated, thereby eliminating embedded description of service and simulation in a mapping from language description to a circuit structure. The method has the advantages: firstly, a TMR design and the fault injection simulation are realized in a unified platform; secondly, coverage-driven and fault type-oriented automatic and random fault injection simulation is supported; thirdly, "plug-and-play" of a fault type database is realized; and fourthly, application of a modeling model can be realized and a reliability index of a quantified chip in a harsh environment is realized.

Description

technical field [0001] The invention relates to fault simulation and injection of integrated circuit fault-tolerant design, in particular to a TMR-based implementation and fault injection simulation platform and simulation method. Background technique [0002] Microelectronics technology has become the main means of implementing embedded electronic systems. With the continuous expansion of application fields, the operating environments of integrated circuit products are becoming more and more diverse. Correspondingly, there are requirements for the adaptability of their operating environments, including Temperature, humidity, smoke, mechanical stress, and space radiation, to name a few. [0003] In the application of space radiation environment, from the electronic system level to the structure level, circuit level and semiconductor physical realization level of chip product development, a variety of fault tolerance and reinforcement methods have been formed to improve the p...

AI Technical Summary

Problems solved by technology

In typical TMR-based implementation and verification, it is necessary to directly implement TMR-type codes, which increases the difficulty of fault-tolerant system design and the probability of design errors

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