High-speed parallel D/A clock synchronization apparatus

A clock synchronization, high-speed technology, applied in the direction of control/adjustment system, instrument, computer control, etc., can solve the problems of channel out of synchronization, difficult synchronization, difficult to guarantee delay time difference, etc., achieve stable synchronous work and solve synchronization problems , the effect of good stability and reliability

Active Publication Date: 2015-11-25
INST OF ELECTRONICS CHINESE ACAD OF SCI
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Problems solved by technology

However, the existing method is applicable when the D/A conversion rate is low. Once high-speed D/A is involved, the signal clock frequency in a synthetic aperture radar (SAR) is a

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  • High-speed parallel D/A clock synchronization apparatus
  • High-speed parallel D/A clock synchronization apparatus

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[0032] In order to make the objectives, technical solutions and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

[0033] The invention discloses a clock synchronization device, which has the characteristics of low jitter and low time offset. By configuring peripheral circuits, the unstable time at the initial moment of triggering is greatly compressed, and the influence of errors caused by clock jitter is effectively overcome, so that multiple signals are generated. The unit is fully working in synchronization.

[0034] The technical solution adopted by the high-speed parallel D / A clock synchronization device of the present invention is to adjust the amplitude level of the input clock signal by configuring the signal conditioning unit circuit, and increase the signal amplitude enough for the post-amplifier before the switch unit is tu...

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Abstract

The invention discloses a high-speed parallel D/A clock synchronization apparatus. The high-speed parallel D/A clock synchronization apparatus comprises a signal conditioning unit for adjusting the amplitude size of clock signals, increasing the amplitude of the clock signals to a saturation degree of an amplification unit before a switch unit is energized and then reducing the amplitude after a state is stable so as to enable the amplification unit to work at a linear interval, and the switch unit and the amplification unit. The invention further discloses a high-speed parallel D/A clock synchronization method. According to the apparatus and method provided by the invention, synchronization of a multichannel signal generation system can only be concentrated on on-off of a radio frequency switch, the transition time at the moment when the switch is turned on and turned off is substantially compressed, the influences of errors caused by clock jittering at D/A conversion initial time, and the stability and the reliability are good. On the other hand, by use of the feature of small noise of a radio frequency circuit, low-noise conversion of high-speed clock signals from a single end to a differential is finished, and the application requirement of circuit difference signals can be met.

Description

technical field [0001] The invention relates to the field of signal generation, in particular to a high-speed parallel D / A clock synchronization device and a synchronization method. Background technique [0002] The high-resolution capability and anti-jamming capability of the radar are closely related to the bandwidth of the radar signal. For example, in order to improve the ranging accuracy and distance resolution, and to image and identify the target, the signal transmitted by the radar is required to have a large bandwidth and time-width product—— A broadband FM signal is added to the wide pulse to expand the signal frequency band and improve the overall performance of the radar. This involves the generation technology of the large bandwidth signal. [0003] At present, linear frequency modulation signal (LFM) is the most widely used signal in most broadband radar systems. With the maturity of digital technology and the rapid development of VLSI technology, direct digit...

Claims

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Application Information

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IPC IPC(8): G05B19/042
CPCG05B19/042G05B2219/25126
Inventor 郭征王岩飞李和平朱建光周以国赵风华
Owner INST OF ELECTRONICS CHINESE ACAD OF SCI
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