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VDMOS device with anti-SEU effect

An anti-single-event effect and device technology, applied in semiconductor devices, electrical components, circuits, etc., can solve the problems of lack of anti-single-event burn-in ability and the concentration of the Pbody area should not be too large, so as to improve the anti-single-event burn-in ability, Improved gate penetration and reduced Miller capacitance

Inactive Publication Date: 2015-12-02
UNIV OF ELECTRONICS SCI & TECH OF CHINA
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Traditional structures such as figure 1 As shown, considering the impact on the device threshold, the concentration of the Pbody region should not be too large, which has no obvious effect on reducing the resistance below the N+ source region of the VDMOS device, and the traditional structure basically does not have the ability to resist single event burnout

Method used

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  • VDMOS device with anti-SEU effect
  • VDMOS device with anti-SEU effect
  • VDMOS device with anti-SEU effect

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Embodiment Construction

[0022] Below in conjunction with accompanying drawing, the technical scheme of the present invention is described in detail:

[0023] A VDMOS device with anti-single event effect of the present invention, such as figure 2 As shown, its cell structure includes a first conductive type semiconductor substrate 9 and a first conductive type semiconductor epitaxial layer 8 located on the upper layer of the first conductive type semiconductor substrate 9; the lower surface of the first conductive type semiconductor substrate 9 is connected to There is a drain metal electrode 10; the first conductive type semiconductor epitaxial layer 8 has a second conductive type semiconductor body region 6 on both sides of the upper layer; the second conductive type semiconductor body region 6 has mutually independent first conductive type semiconductors The source region 5 and the second conductive type semiconductor body contact region 7; the first conductive type semiconductor epitaxial layer 8...

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Abstract

The invention belongs to the power semiconductor device technical field, and concretely relates to a VDMOS device with an anti-SEU effect. In the technical scheme, an epitaxial layer under a grid electrode is internally provided with a second conductive semiconductor column connected to a source electrode to generate a transverse electric field and to change a cavity passing path, thereby avoiding SEGR and SEB caused by parasitic transistor starting, and improving the anti-SEU capability of a VDMOS device. The VDMOS device with an anti-SEU effect has greatly improved anti-SEGR and anti-SEGR capabilities; in addition, the invention provides a VDMOS device with an anti-SEU radiation effect, which effectively reduces device conduction resistance under the condition of guaranteeing a shorting voltage; meanwhile, the Miller capacitance of a VDMOS structure is substantially reduced thanks to a coverage area with a reduced grid electrode.

Description

technical field [0001] The invention belongs to the technical field of power semiconductor devices, and relates to a VDMOS (Vertical Double Diffused Metal-Oxide Semiconductor Field Effect Transistor) device with anti-single particle effect. Background technique [0002] With the rapid development of power electronic technology to the field of high frequency and high power applications, VDMOS has become one of the irreplaceable important devices in the field of power electronics, and the number of power electronic circuits using VDMOS is increasing. The structural device is usually formed by secondary diffusion or ion implantation technology. It is a multi-cell device, which is easy to integrate, has a high power density, and has many sub-conductivity and good frequency characteristics. At present, VDMOS is one of the mainstream devices of power MOS. As a power switch, VDMOS has the advantages of high withstand voltage, fast switching speed, low on-resistance, low driving po...

Claims

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Application Information

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IPC IPC(8): H01L29/78H01L29/06
CPCH01L29/0603H01L29/0684H01L29/7802H01L29/783
Inventor 任敏蔡果杨珏琳曹晓峰陈哲李爽李泽宏张金平高巍张波
Owner UNIV OF ELECTRONICS SCI & TECH OF CHINA