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A vdmos device with anti-single event effect

An anti-single-event effect and device technology, applied in semiconductor devices, electrical components, circuits, etc., can solve the problems of not having the ability to resist single-event burnout, and the concentration of the Pbody area should not be too large, so as to improve the anti-single-event burnout ability, Improved gate penetration and reduced on-resistance

Inactive Publication Date: 2018-05-15
UNIV OF ELECTRONICS SCI & TECH OF CHINA
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Traditional structures such as figure 1 As shown, considering the impact on the device threshold, the concentration of the Pbody region should not be too large, which has no obvious effect on reducing the resistance below the N+ source region of the VDMOS device, and the traditional structure basically does not have the ability to resist single event burnout

Method used

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  • A vdmos device with anti-single event effect
  • A vdmos device with anti-single event effect
  • A vdmos device with anti-single event effect

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Embodiment Construction

[0022] Below in conjunction with accompanying drawing, describe technical scheme of the present invention in detail:

[0023] A VDMOS device with anti-single event effect of the present invention, such as figure 2 As shown, its cellular structure includes a first conductivity type semiconductor substrate 9 and a first conductivity type semiconductor epitaxial layer 8 located on the upper layer of the first conductivity type semiconductor substrate 9; the lower surface of the first conductivity type semiconductor substrate 9 is connected to There is a drain metal electrode 10; the first conductivity type semiconductor epitaxial layer 8 has a second conductivity type semiconductor body region 6 on both sides of the upper layer; the second conductivity type semiconductor body region 6 has mutually independent first conductivity type semiconductor The source region 5 and the second conductivity type semiconductor body contact region 7; the upper surface of the first conductivity ...

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Abstract

The invention belongs to the technical field of power semiconductor devices, and in particular relates to a VDMOS device with anti-single event effect. The main technical solution of the present invention is that the adopted technical solution is mainly to arrange a second conductivity type semiconductor column connected to the source in the epitaxial layer under the gate to generate a lateral electric field and change the flow path of holes, thereby avoiding the occurrence of parasitic The phenomenon of single-event burnout and single-event gate-through phenomenon caused by transistor turn-on improves the anti-single-event capability of VDMOS devices. The beneficial effect of the present invention is that the anti-single-event burn-out ability of VDMOS is greatly improved, and the anti-single-event gate-through ability can also be well improved; in addition, the anti-single-event irradiation VDMOS device proposed by the present invention is guaranteed Under the premise of the breakdown voltage, the on-resistance of the device is effectively reduced; at the same time, due to the reduced coverage area of ​​the gate electrode, the Miller capacitance of the VDMOS structure is greatly reduced.

Description

technical field [0001] The invention belongs to the technical field of power semiconductor devices, and relates to a VDMOS (vertical double-diffused metal-oxide semiconductor field-effect transistor) device with anti-single event effect. Background technique [0002] With the rapid development of power electronics technology to high-frequency and high-power applications, VDMOS has become one of the irreplaceable important devices in the field of power electronics, and power electronic circuits using VDMOS are increasing. The device with this structure is usually formed by secondary diffusion or ion implantation technology. It is a multi-cell device, easy to integrate, high power density, multi-carrier conduction, and good frequency characteristics. At present, VDMOS is one of the mainstream devices of power MOS. As a power switch, VDMOS has the advantages of high withstand voltage, fast switching speed, low on-resistance, low drive power, good thermal stability, low noise a...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L29/78H01L29/06
CPCH01L29/0603H01L29/0684H01L29/7802H01L29/783
Inventor 任敏蔡果杨珏琳曹晓峰陈哲李爽李泽宏张金平高巍张波
Owner UNIV OF ELECTRONICS SCI & TECH OF CHINA