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A trench-gate MOS device with improved resistance to single event burnout

A MOS device, anti-single particle technology, applied in semiconductor devices, electrical components, diodes, etc., can solve the problems of poor anti-single particle burnout ability and the concentration of Pbody area cannot be too large, and achieve the effect of improving the anti-single particle burnout ability

Active Publication Date: 2020-11-13
UNIV OF ELECTRONIC SCI & TECH OF CHINA
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Considering the impact on the device threshold, the concentration of the Pbody region should not be too large, which has no obvious effect on reducing the resistance below the N+ source region of the VDMOS device, so the traditional structure has poor resistance to single event burnout

Method used

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  • A trench-gate MOS device with improved resistance to single event burnout
  • A trench-gate MOS device with improved resistance to single event burnout
  • A trench-gate MOS device with improved resistance to single event burnout

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0019] Such as figure 1 As shown, in this example, a trench gate MOS device with improved resistance to single event burnout has a cell structure including a drain metal electrode 1, a first conductivity type semiconductor substrate 2, a first conductivity type type semiconductor epitaxial layer 3 and source metal electrode 10; the upper layer of the first conductivity type semiconductor epitaxial layer 3 has a second conductivity type semiconductor body region 6, a first conductivity type semiconductor source region 7, a second conductivity type semiconductor body contact region 8 and groove gate; the second conductivity type semiconductor body contact region 8 is located between the first conductivity type semiconductor source region 7, and on the first conductivity type semiconductor source region 7 and the second conductivity type semiconductor body contact region 8 The surface is connected to the source metal electrode 10; the second conductivity type semiconductor body r...

Embodiment 2

[0026] Such as Figure 6 As shown, the structure of this example is based on Embodiment 1, adding one or more second conductivity type current guiding regions on the side of the low resistance second conductivity type semiconductor pillar 11, which can further improve the resistance to single event burning ability.

Embodiment 3

[0028] Such as Figure 7 As shown, the structure of this example is based on Example 1, replacing the second conductivity type semiconductor column 11 and the metal electrode with a highly doped second conductivity type semiconductor region and a second conductivity type semiconductor region containing a large number of recombination centers 12.

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PUM

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Abstract

A trench MOS device with improved single event burnout endurance, applied in the field of semiconductor. The device is provided, in an epitaxial layer, with a conductive type semiconductor pillar connected to a source and a second conductive type current-directing region. Whereby, the trajectory of the electron-hole pairs induced by the single event effect is changed and thus avoids the single event burnout caused by the triggering of parasitic transistors, therefore improving the endurance of the single event burnout of the trench MOS device.

Description

technical field [0001] The invention belongs to the technical field of semiconductors, and relates to a trench gate MOS device which improves the anti-single-event burning capability. Background technique [0002] With the rapid development of power electronics technology to high-frequency and high-power applications, VDMOS has become one of the irreplaceable important devices in the field of power electronics. The device with this structure is usually formed by secondary diffusion or ion implantation technology. It is a multi-cell device, easy to integrate, high power density, multi-carrier conduction, and good frequency characteristics. However, due to the large gate-source capacitance in the power VDMOS, the switching rate of the device is limited. At the same time, due to the junction field effect transistor (JFET) inside the VDMOS device, the resistance of the JFET limits the saturation current density inside the device. In the field of low-voltage and low-power MOS d...

Claims

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Application Information

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IPC IPC(8): H01L29/78
CPCH01L29/0619H01L29/0623H01L29/0646H01L29/41766H01L29/7805H01L29/7813H01L29/4236
Inventor 任敏林育赐谢驰苏志恒李泽宏张金平高巍张波
Owner UNIV OF ELECTRONIC SCI & TECH OF CHINA