On-chip network multi-core framework

Abstract

The invention relates to an on-chip network multi-core framework. The on-chip network multi-core framework comprises an on-chip network multi-core framework body, wherein the on-chip network multi-core framework body comprises multiple calculation units, a router and a network interface, the multiple calculation units are connected with the network interface through the router to realize parallel data processing and data interaction, one of the calculation units is taken as a main control core node, others are taken as operation core nodes, the main core node is for off-chip data exchange, the data is transmitted by the operation core nodes to the main control core node, exchange of the off-chip data is accomplished through the main control core node; storage spaces of the multiple calculation units employ unified addressing, so a core of each calculation unit can access the storage space of any calculation unit. According to the on-chip network multi-core framework, mass-scale data transmission can be realized among the calculation units, carrying data of the network interface can be realized, an on-chip network resource utilization rate is improved, power consumption is reduced, and calculation efficiency and on-chip network performance of a multi-core processor system can be improved.

Description

technical field [0001] The invention relates to the field of network-on-chip technology, in particular to a network-on-chip multi-core architecture. Background technique [0002] With the development of microelectronic computing technology, the integration of VLSI is getting higher and higher, and the drawbacks of the system-on-chip (SOC) bus structure are gradually exposed. Problems such as physical connection and clock delay caused by a single clock restrict SOC Therefore, in 1999, academic institutions represented by the Royal Swedish Institute of Technology proposed a new communication architecture-NOC. This design combines the concept of communication network into integrated circuit design, and each computing unit module is a network on chip. a routing node for . In the traditional SOC design, the bus architecture is used to connect various modules and a unified clock is used. Although this solution is still feasible in the case of low integration of SOC, with the con...

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Problems solved by technology

Although this solution is still feasible in the case of low integration of SOC, with the continuous improvement of integration, SOC is affected by serious clock delay and skew, which brings great challenges to designers. Network on Chip (NOC ) completely solves this problem. The NOC system adopts a distributed network structure. They do not have a unified clock. Each computing unit is connected through a router. They are independent of each other and can work completely independently.

[0003] The SOC communication efficiency of the traditional bus structure is relatively low, and it cannot truly realize multi-processor parallel processing of communication tasks, which makes the traditional bus structure encounter an insurmountable communication bottleneck. The main performance is as follows:

[0004] (1) Difficulty in scalability: With the development of technology, the requirements of big data computing will increase the number of processors on the chip, and the communication volume between processors will also increase, resulting in SOC bus address resources and processors. Mismatch between the numbers, and limited address resources limit the increase in the number of processors

[0005] (2) Parallel communication is not possible: the bus structure is used in the SOC. Although the bus structure is a shared interconnection structure, when multiple processors send requests at the same time, the bus will generate arbitration according to the priority, which leads to system Cannot communicate in parallel, resulting in inefficient system communication

[0006] (3) Single clock synchronization problem: SOC requires global synchronization of signals under the bus structure. As the process characteristics and frequency requirements become higher and higher, the interconnection delay under the bus structure makes the problem of clock misalignment difficult to control. Single clock synchronization is completely The work of the chip has become extremely difficult, so it is urgent to propose a new interconnection mechanism to replace the traditional bus mechanism

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