Data processing method and electronic device

Abstract

The invention discloses a data processing method and an electronic device. The method comprises: based on a priority of instructions in an instruction queue buffer, selecting an executable instruction, and aimed at the selected instruction, transmitting a bus request to request for a bus; when the bus is received by the request, transmitting the executable instruction to a corresponding target memory unit in a memory by using the bus, reading timing information of the executable instruction to a polling queue buffer; when random timing information in the polling queue buffer is arrived, transmitting the bus request to request for the bus, so that when the bus is received by the request, by using the bus, whether the target memory unit corresponding to the instruction that the timing information belongs to is executed is inquired; and when the bus is free, based on a preset policy, performing arbitration on the received bus, and based on an arbitration result, distributing the bus. By implementing the data processing method, out-of-order execution of the instructions in the memory units can be implemented in an efficient and low-power way, thus increasing the bus utilization rate and further increasing the read and write speed of the memory.

Description

technical field [0001] The invention relates to storage technology, in particular to a data processing method and electronic equipment. Background technique [0002] Electronic devices such as smartphones and tablet computers generally use flash memory (Flash) such as NANDflash and other storage units as storage media. The top-down architecture of flash memory is: chip (Chip), logic unit (LU), slice (Plane), block (Block), page (Page), each upper-level structure (except the bottom layer) can include one or more lower-level structures, for example, a chip can include one or more logical units; where the logical unit can use a logical unit number ( LUN, LogicUnitNumber) identification, the block is the basic unit of erasing in the flash memory, and the page is the basic addressing unit (that is, the page is the basic unit of the read operation). Among them, the logic unit is an instruction that can independently respond to the processor The smallest (basic) unit of ; [0003...

AI Technical Summary

Problems solved by technology

[0006] 1) Implementation through microcode requires a large cache (SRAM), and requires a separate SRAM space for each logic unit operation channel; at the same time, the microcode design is complex and difficult to modify, and it is relatively difficult to implement out-of-order execution of different instructions. Disaster;

[0007] 2) It is implemented through processor (CPU) scheduling, requires the processor to maintain the queue, interact with the flash memory through interrupts, and need to query the status of the flash memory, so the speed is limited, it is not suitable for occasions with high bandwidth requirements, and the real-time performance is poor. The processor performance requirements are also high, resulting in high power consumption of the processor

[0008] To sum up, there is no effective solution in the relevant technologies for realizing the out-of-order execution of instructions in an efficient and low-power way to improve the utilization of the bus and thereby increase the read and write speed of the flash memory.

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