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Memory circuit based on resistance random access memory (RRAM) cells

A storage circuit and resistive storage technology, applied in information storage, static memory, digital memory information and other directions, can solve problems such as unavailability, and achieve the effect of improving repair opportunities, improving repair success rate, and providing feasibility

Active Publication Date: 2016-01-20
XI AN UNIIC SEMICON CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

For chips developed based on certain processes that do not support eFUSE technology, this technology cannot be used to achieve the above functions
[0008] 2. eFUSE technology supports eFUSE programming after the chip leaves the factory to change the internal circuit, but this operation is a one-time programming, so there is only one chance to repair the relevant circuit, which has certain limitations

Method used

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  • Memory circuit based on resistance random access memory (RRAM) cells
  • Memory circuit based on resistance random access memory (RRAM) cells
  • Memory circuit based on resistance random access memory (RRAM) cells

Examples

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Embodiment Construction

[0040] On-chip multi-data storage scheme of the present invention such as figure 2 As shown, it mainly includes storage array, instruction decoder, row control module, column control module and test module.

[0041] The instruction decoder is a combinational logic circuit, which is used to receive the operation instruction and complete the decoding of the operation instruction, so as to realize the corresponding operation on the internal storage array. The operating instructions in the present invention mainly include four operations: set (write 0), reset (write 1), read (read stored data), and readr (read RRAM unit organization). The purpose of the set and reset instructions is to perform low-resistance operation and high-resistance operation on the selected RRAM cell respectively to realize the writing of data 0 or 1. Due to the repeatability of the RRAM unit, the operator can implement multiple write operations to the storage unit in the array through the set / reset comman...

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PUM

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Abstract

The invention relates to a memory circuit based on resistance random access memory (RRAM) cells. The memory circuit comprises a row control module, a column control module, a memory array, an instruction decoder and a test module. The memory array comprises multiple memory cells and a zone bit memory cell, and each memory cell comprises one RRAM cell, a sensitive amplifier, a reference resistance circuit and a data path. The zone bit memory cell is used for embodying whether zone bits are written in the memory cells or not, the sensitive amplifiers are finally in a high-voltage state or a low-voltage state according to resistance values of the two ends, the data paths are used for being connected with a circuit to be repaired and the test module through an output port fuseq, the output ends of all row control cells are connected with all the row memory cells, and the output ends of all column control cells are connected with all the column memory cells. The technical problems that an existing eFUSE technology provides limit technical support and has the limitation that repairing can be carried out only once are solved. The memory circuit is capable of replacing the eFUSE technology and achieving the memory technology of multiple programming operations.

Description

technical field [0001] The invention relates to a storage circuit based on a resistive storage unit RRAM which can replace eFUSE technology. Background technique [0002] With the rapid development of the information age, the development of integrated circuits is also increasing rapidly, and the design level is improving day by day. The function and logic complexity of VLSI and system-on-chip chips are also increasing. On the other hand, in order to pursue low power consumption and high integration, the manufacturing process of chips is becoming more and more complicated, which makes chips more prone to defects in the manufacturing process, especially in memory chips, which inevitably exist after leaving the factory. More or less damaged memory cells, or defective logic functions, reduce the yield rate and increase the cost of chip design and development. Therefore, in chip development, redundant units are generally added to achieve subsequent replacement of defective parts...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C13/00
Inventor 王小光
Owner XI AN UNIIC SEMICON CO LTD