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ddr controller and control method based on fpga

A controller and control unit technology, applied in the direction of instruments, electrical digital data processing, etc., can solve the problems of difficult to meet requirements for special use, inability to flexibly configure, increase user costs, etc., to reduce technical risks, improve flexibility, and occupy resources. less effect

Inactive Publication Date: 2017-12-01
CHINA ELECTRONIS TECH INSTR CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

As the manufacturer's own dedicated IP core, the FPGA core will charge users fees and increase user costs. On the other hand, it is not flexible enough to use and can only be used as a general data cache control interface. It is difficult to meet the requirements for special applications. The pins of the IP core FPGA are fixed and cannot be flexibly configured, which puts forward high requirements for the layout and wiring of the printed board

Method used

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  • ddr controller and control method based on fpga
  • ddr controller and control method based on fpga

Examples

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Embodiment Construction

[0040] Below in conjunction with accompanying drawing and specific embodiment the present invention is described in further detail:

[0041] combine figure 1 As shown, the FPGA-based DDR controller includes:

[0042] The state machine is configured to complete the timing control function of the DDR controller, realize correct access to the DDR memory, and switch between corresponding states according to the access requirements;

[0043] The configuration control unit is configured to configure the DDR memory register when powering on;

[0044] an activation control unit configured to activate the data array of the DDR memory;

[0045] The read-write control unit is configured to perform synchronous processing on external access, give a read-write flag, and judge whether it is a burst read-write or a single-cycle read-write;

[0046] a pre-charging control unit configured to perform an invalid operation on the activated row unit;

[0047] a refresh control unit configured t...

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PUM

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Abstract

This invention discloses a DDR controller and controlling method based on FPGA. The controller comprises a state machine, a configuration control unit, an activation control unit, a read-write control unit, a precharge control unit, a refresh control unit and a port control unit; the state machine is used for completing time sequence control function of the DDR controller, realizing access to a DDR memory, and switching between corresponding states according to access requirements; the configuration control unit is used for configuring when the DDR memory is powered on; the activation control unit is used for activating data arrays of the DDR memory; the read-write control unit is used for synchronously processing external access, giving a read-write mark, and judging whether the read-write mark is burst read-write or single-period read-write; the precharge control unit is used for completing invalid operation to activated row unit; the refresh control unit is used for charging the data arrays; and the port control unit is used for latching ports of a data bus, an address bus and a control bus. The method provided by the invention is beneficial to solve the problem for controlling the DDR memory.

Description

technical field [0001] The invention relates to an FPGA-based DDR controller and an FPGA-based DDR control method. Background technique [0002] DDR memory has the characteristics of miniaturization and large capacity, and is widely used in CPU systems, data acquisition systems and other fields as data memory. In the field of data acquisition systems, it is mainly used as a data cache. How to realize the control of DDR memory so that it can meet the requirements of data cache, usually use the FPGA core generator to realize the control of DDR memory and complete the reading, writing, refreshing, and processing of DDR memory. Pre-charging, power-on configuration and other operations. As the manufacturer's own dedicated IP core, the FPGA core will charge users and increase user costs. On the other hand, it is not flexible enough to use and can only be used as a general data cache control interface. It is difficult to meet the requirements for special use. The pins of the IP c...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F13/16G06F13/38
CPCG06F13/1668G06F13/385
Inventor 栗永强张永坡布乃红戚瑞民王俊生
Owner CHINA ELECTRONIS TECH INSTR CO LTD
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