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DLL locking process circuit and method for improving DRAM self-refreshing and exiting

A locking circuit and self-refresh technology, applied in static memory, digital memory information, information storage, etc., can solve the problem of long locking time of DRAM memory, improve immunity, reduce noise interference, and avoid noise interference. Effect

Active Publication Date: 2016-01-27
XI AN UNIIC SEMICON CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0027] In order to solve the technical problem that the DLL locking operation of the existing DRAM memory has a long locking time after self-refresh exit, the invention provides a DLL lock circuit and a locking method for improving the self-refresh exit of the DRAM memory. The purpose of the invention is to improve DRAM The DLL (Digital Delay Locked Loop) locking process of the memory after self-refresh exit, thereby improving the anti-interference ability of the memory after self-refresh exit

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  • DLL locking process circuit and method for improving DRAM self-refreshing and exiting

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Embodiment Construction

[0049] Improve the DLL lock circuit for DRAM memory self-refresh exit, including registers, delay units and slow control circuits,

[0050] The register is used to record the number N of delay units locked by the DLL output circuit when the DRAM memory enters the self-refresh state;

[0051] The delay unit is used to start the DLL output circuit to start locking after a period of delay when the DRAM memory exits the self-refresh state;

[0052] The slow control circuit is used to set the number of DLL delay units to N according to the number N of delay units recorded in the register when the DLL output circuit starts to lock, and then slowly adjust the number of DLL delay units according to the output control signal of the DLL phase detector .

[0053] The slow speed is adjusted by one step for 8-32 cycles of the input clock clk2dll, and the step frequency is 5-20ps.

[0054] The length of the time delay of the delay unit is less than the locking time configured by the exter...

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Abstract

The invention relates to a DLL locking process circuit and method for improving DRAM self-refreshing and exiting. The circuit comprises a register, delay units and a low speed control circuit. The register is used for recording the number N of the delay units locked by a DLL output circuit when a DRAM enters a self-refreshing and exiting state; the delay units are used for delaying a period of time when the DRAM exits from the self-refreshing state, and then the DLL output circuit starts to perform locking; the slow speed control circuit is used for setting the number of DLL delay units to be N according to the number N, recorded by the register, of the delay units when the DLL output circuit starts to perform locking, and then adjusting the number of the DLL delay units at a low speed according to DLL phase discriminator output control signals. The technical problem that DLL locking operation is long in locking time after an existing DRAM exits from self-refreshing is solved, and the self-refreshing and exiting antijamming capability of the memory is improved.

Description

technical field [0001] The invention belongs to the field of semiconductor DRAM chip design, and in particular relates to a DLL locking process circuit and a locking method for improving the self-refresh exit of DRAM memory. Background technique [0002] Computers and various electronic devices are widely used in all aspects of modern life, and the demand for semiconductor DRAM chips is increasing. People's requirements for speed are getting faster and faster, and DRAM chips have higher and higher requirements for the system. Small disturbances generated by the system or the chip itself will cause memory failures. Therefore, it is more and more important to improve the anti-interference ability of the memory. [0003] Such as figure 1 As shown, the basic architecture of DLL in commonly used DRAM memory: including input clock receiver, DLL delay unit, first DCC delay unit, second DCC delay unit, DCC phase detector, output clock generation circuit, clock path feedback circui...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C11/4063H03L7/08
Inventor 亚历山大
Owner XI AN UNIIC SEMICON CO LTD