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Edge oxide layer stripping device and wafer edge oxide layer stripping method

An oxide layer and edge technology, used in electrical components, semiconductor/solid-state device manufacturing, circuits, etc., can solve problems such as excessive etching, insufficient etching, poor wafer process and electrical properties, and achieve yield improvement and avoidance. The effect of under-etching

Active Publication Date: 2018-01-30
KUNSHAN ZHONGCHEN SILICON CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

This advantage is that the oxide layer on the other side of the wafer can be completely preserved, but the disadvantage is that the oxide layer on both sides is difficult to control the amount of etching, and it is easy to form under etching or over etching.
This will have a negative impact on the process and electrical properties of subsequent wafers

Method used

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  • Edge oxide layer stripping device and wafer edge oxide layer stripping method
  • Edge oxide layer stripping device and wafer edge oxide layer stripping method
  • Edge oxide layer stripping device and wafer edge oxide layer stripping method

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Experimental program
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Embodiment Construction

[0036] refer to figure 2 , a schematic diagram of the device for stripping the edge oxide layer of the present invention. Such as figure 2 As shown, the device for stripping the edge oxide layer of the present invention includes a stripper body 10 and a gas mask 20 . The stripper body 10 includes a carrier body 11 , a carrier plate 13 , an input end 15 , and an output end 17 . The carrier tray 13 is disposed in the carrier body 11 for placing a wafer 200 . The surface of the wafer 200 without the oxide layer faces upward, and the surface with the oxide layer faces downward. The placement of the wafer 200 can be accomplished by a robotic arm (not shown in the figure). The input end 15 communicates with the carrier body 11 for inputting a protective liquid. The output end 17 communicates with the bearing body 11 for discharging the protection liquid. The wafer 200 may be a silicon wafer or a sapphire wafer, the protection liquid may be deionized water, and the carrier pl...

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PUM

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Abstract

The invention provides an edge oxide layer stripping device and a stripping method of a wafer edge oxide layer. The device comprises a stripper body and a gas cover. The stripper body comprises a bearing body, a bearing disk, an input end and an output end. The method comprises the steps of: providing a wafer input protection liquid so as to cover a reserved area of a wafer oxide layer; exposing the wafer edge oxide layer to be removed; forming an enclosed space; inputting fluorine-contained etching gas to the enclosed space; enabling the fluorine-contained gas to act with the edge oxide layer so as to strip the edge oxide layer; and continuously replacing the protection liquid to enable the great reduction of the protection liquid due to the influence of the fluorine-contained etching gas. According to the invention, the etched edge oxide layer is precisely controlled, and the yield rate of a subsequent epitaxial process is substantially improved.

Description

technical field [0001] The invention relates to a device for stripping an edge oxide layer and a method for stripping an edge oxide layer of a wafer, in particular to a device for stripping an edge oxide layer and a method for stripping an edge oxide layer of a wafer using the device. Background technique [0002] refer to figure 1 , a schematic cross-sectional view of a wafer in the prior art. Such as figure 1 As shown, usually in order to prevent the diffusion of doping atoms in the wafer 200 , an oxide layer 210 is usually formed on a surface of the wafer 200 . When forming the oxide layer 210, the SiH 4 Formed by reaction with oxygen. [0003] Generally, epitaxy is continued on the front side 220 of the wafer 200 , and the oxide layer 210 is not formed. However, when the oxide layer 210 is formed, the oxide layer 210 usually extends to the edge of the front side 220, forming, for example, figure 1 The edge oxide layer 211 below the center line C of the middle wafer...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/311H01L21/67
CPCH01L21/311H01L21/67
Inventor 范俊一林塘棋徐文庆
Owner KUNSHAN ZHONGCHEN SILICON CO LTD