Preparation method of integrated circuit chip failure analysis sample

Abstract

The invention relates to a preparation method of an integrated circuit chip failure analysis sample. The method includes the following steps: smearing a packaging glue on the integrated circuit chip sample to cover the part required for failure analysis by the packaging glue; heat-curing the sample with packaging glue; and polishing the cured sample until part requiring failure analysis. The method uses cured packaging glue to strengthen the part requiring failure analysis, so as to avoid deformation in the polishing process, and preserve the original appearance. The preparation process does not need expensive equipment and the preparation conditions can be met easily.

Description

technical field [0001] The invention relates to a semiconductor device, in particular to a method for preparing an integrated circuit chip failure analysis sample. Background technique [0002] Due to manufacturing cost considerations, copper wires are used by more and more companies in the wire bonding process of integrated circuit (IC) chips. However, the inherent hardness and easy corrosion of copper wires make the copper wire bonding process have higher requirements on the aluminum thickness of the chip, and failure phenomena such as peeling, craters, and cracks are also prone to occur during the bonding process. Therefore, the demand for failure analysis for copper wire bonding failure is also increasing. Sectional morphology analysis is a commonly used analysis method, and a traditional solution is to polish and observe the morphology after packaging the die. [0003] However, generally only packaging factories have the ability to package chips, and WaferFoundry's fa...

AI Technical Summary

Problems solved by technology

[0003] However, generally only the packaging factory has the ability to package the chip, WaferFoundry's failure analysis laboratory does not have special packaging equipment

Images