Read-only register verification test platform and verification method based on UVM (Universal Verification Methodology Manual)

Abstract

The invention discloses a read-only register verification test platform based on a UVM (Universal Verification Methodology Manual). The read-only register verification test platform comprises a test frame based on the UVM and a design module to be tested, wherein the test frame comprises a UVM test sequence and a UVM sequence generator; the design module to be tested is a digital design module provided with a register and a register read-write bus interface; the test frame based on the UVM is connected with the design module to be tested through the register read-write bus interface; the UVM test sequence can call the UVM sequence generator; the UVM sequence generator drives the design module to be tested through the register read-write bus interface; and the UVM test sequence carries out assignment rewriting on an internal signal of the design module to be tested through a VPI (Verilog Programming Interface). The invention also discloses a read-only register verification method based on the UVM. Verification efficiency can be effectively improved, and a verification confidence level is improved.

Description

technical field [0001] The invention relates to the field of chip verification, in particular to a read-only register verification test platform based on UVM (Universal Verification Methodology Manual). The invention also relates to a read-only register verification method based on UVM verification methodology. Background technique [0002] In chip design, registers are often used to configure chip parameters and control chip functions. According to the specific functions of the chip, the read and write attributes of each register are different. Since some registers with read-only attributes can only be read through the bus, it is impossible to verify whether the data of each bit of the register can be read correctly; and the UVM test sequence in the UVM verification methodology is generally placed in a package. It is impossible to see the internal hierarchy of DUT (design under test) in the package, that is, it is impossible to directly rewrite register values ​​through cr...

AI Technical Summary

Problems solved by technology

Since some registers with read-only attributes can only be read through the bus, it is impossible to verify whether the data of each bit of the register can be read correctly; and the UVM test sequence in the UVM verification methodology is generally placed in a package. It is impossible to see the internal hierarchy of DUT (design under test) in the package, that is, it is impossible to directly rewrite register values ​​through cross-module references; therefore, using traditional methods to verify read-only registers, verifiers have to spend a lot of time rewriting the test platform and test sequence

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