Read-only register verification test platform and verification method based on UVM (Universal Verification Methodology Manual)

A verification methodology and verification test technology, applied in the field of read-only register verification and read-only register verification test platform, can solve the problems of unable to see the DUT hierarchy, rewrite register values, unable to verify the correct reading of register data, etc. Increase verification reliability, facilitate construction, reduce programming volume and programming difficulty

Inactive Publication Date: 2016-03-30
SHANGHAI HUAHONG INTEGRATED CIRCUIT
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  • Abstract
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Problems solved by technology

Since some registers with read-only attributes can only be read through the bus, it is impossible to verify whether the data of each bit of the register can be read correctly; and the UVM test sequence in the UVM verification methodology is generally placed in a package. It is impossible to see the inter

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  • Read-only register verification test platform and verification method based on UVM (Universal Verification Methodology Manual)
  • Read-only register verification test platform and verification method based on UVM (Universal Verification Methodology Manual)

Examples

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Example Embodiment

[0015] Such as figure 1 As shown, the UVM test sequence is imported into the C subroutine uvm_hdl_deposit through DPI (direct programming interface); the UVM test sequence is passed uvm_hdl_deposit(stringhdl_path, inputuvm_hdl_data_tvalue; string indicates that the incoming hdl_path parameter is a string type, and hdl_path stores a register Hierarchical path; input indicates that the following value variable is subroutine input, uvm_hdl_data_t indicates the data type of value, the data type is a data type defined in uvm, which is equivalent to register type data, and value is the value that will eventually be stored in the register) The task calls the C function vpi_put_value of the VPI interface, according to the hierarchical relationship of the read-only register in the DUT [or as figure 2 As shown, the value of the read-only register is rewritten through the incoming register hierarchy path (hdl_path)]. The UVM test sequence introduced above cannot directly reference the in...

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Abstract

The invention discloses a read-only register verification test platform based on a UVM (Universal Verification Methodology Manual). The read-only register verification test platform comprises a test frame based on the UVM and a design module to be tested, wherein the test frame comprises a UVM test sequence and a UVM sequence generator; the design module to be tested is a digital design module provided with a register and a register read-write bus interface; the test frame based on the UVM is connected with the design module to be tested through the register read-write bus interface; the UVM test sequence can call the UVM sequence generator; the UVM sequence generator drives the design module to be tested through the register read-write bus interface; and the UVM test sequence carries out assignment rewriting on an internal signal of the design module to be tested through a VPI (Verilog Programming Interface). The invention also discloses a read-only register verification method based on the UVM. Verification efficiency can be effectively improved, and a verification confidence level is improved.

Description

technical field [0001] The invention relates to the field of chip verification, in particular to a read-only register verification test platform based on UVM (Universal Verification Methodology Manual). The invention also relates to a read-only register verification method based on UVM verification methodology. Background technique [0002] In chip design, registers are often used to configure chip parameters and control chip functions. According to the specific functions of the chip, the read and write attributes of each register are different. Since some registers with read-only attributes can only be read through the bus, it is impossible to verify whether the data of each bit of the register can be read correctly; and the UVM test sequence in the UVM verification methodology is generally placed in a package. It is impossible to see the internal hierarchy of DUT (design under test) in the package, that is, it is impossible to directly rewrite register values ​​through cr...

Claims

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Application Information

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IPC IPC(8): G06F11/26
Inventor 茅乾博
Owner SHANGHAI HUAHONG INTEGRATED CIRCUIT
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