Etching method
A mask layer and hardening layer technology, which is applied in the direction of electrical components, semiconductor/solid-state device manufacturing, circuits, etc., can solve the problems of increasing process steps, increasing process costs, and limiting the size of pattern openings, etc.
Active Publication Date: 2016-03-30
SEMICON MFG INT (SHANGHAI) CORP
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Problems solved by technology
[0007] But only by increasing the number of times of the photolithography and etching processes, not only increase the process steps, but also increase the process cost
In addition, the final size of the wafer 10 is also limited by the size of the pattern opening in the photoresist mask.
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[0034] As mentioned in the background, as the feature size of semiconductor devices becomes smaller and smaller, the integration level of semiconductor devices continues to increase, which puts forward new requirements for reducing the size of semiconductor components. For this reason, it is a new challenge to break through the limitations of the existing instrument precision and material characteristics to further reduce the opening size in the semiconductor substrate.
[0035] To this end, the present invention provides an etching method, comprising: after forming a first mask layer on a semiconductor substrate, forming a second mask layer on the first mask layer, and forming a second mask layer on the second mask layer After forming the first opening in the mold layer, harden the first mask layer exposed in the first opening to form a hardened layer in the first mask layer; then engrave along the first opening etching the hardened layer, forming a second opening in the hard...
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The invention provides an etching method. The etching method comprises the steps of: forming a first mask layer on a semiconductor substrate; then forming a second mask layer on the first mask layer; and after a first opening is formed in the second mask layer, carrying out hardening processing on the first mask layer exposed from the first opening; and forming a hardened layer in the first mask layer; then etching the hardened layer along the first opening, and forming a second opening in the hardened layer; based on the fact that the hardened layer is relatively large in hardness, enabling the etching speed of the hardened layer close to the side wall part of the first opening to be smaller than the etching speed of the hardened layer close to the center part of the first opening, thereby ensuring that the second opening has an inclined side wall and the size of the top end is larger than the size of the bottom part; and then using the residual hardened layer as a mask to etch the semiconductor substrate and form a third opening, and effectively reducing the size of the third opening.
Description
technical field [0001] The invention relates to the technical field of semiconductors, in particular to an etching method. Background technique [0002] Photolithography and etching steps are very important processes in the semiconductor manufacturing process. refer to figure 1 , shows a schematic diagram of a photolithography process in the prior art. The photolithography process includes: after forming a photoresist layer on the wafer 10, exposing and developing the photoresist layer, transferring the pattern on the mask plate to the photoresist layer, thereby forming a photoresist mask 11 , figure 1 The photoresist mask described in has pattern openings 12 . Etching refers to the process of using the photoresist mask 11 as a mask to etch the wafer 10 along the pattern opening 12 to form a pattern in the wafer 10 . [0003] With the development of semiconductor technology, the critical dimension (Critical Dimension, CD) of semiconductor devices is getting smaller and ...
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IPC IPC(8): H01L21/311
Inventor 单朝杰
Owner SEMICON MFG INT (SHANGHAI) CORP