Shift register unit and driving method, gate drive circuit and array substrate thereof

Abstract

The invention provides a shift register unit, a driving method, a gate drive circuit, an array substrate and a display device. N auxiliary output modules are sequentially connected at the output end of the shift register module in series and are used for enabling output level to produce N + 1 times of jump rise from the Nth time period before an output time period to the output time period and finally outputting shift register signals in the output time period, wherein the N is a integer greater than or equal to 1. Compared with the prior art, the drive voltage of GOA can be reduced, accordingly the charge-discharge power consumption of the a CLOCK to a stray capacitor of a GOA logical circuit is reduced, the purpose of reducing the logic consumption of the GOA is achieved, further the power consumption and driving requirements of a panel can be reduced, and the stability of the products can be improved.

Description

technical field [0001] The invention belongs to the technical field of liquid crystal display, and in particular relates to a shift register unit, a driving method thereof, a gate driving circuit, an array substrate, and a display device. Background technique [0002] GOA technology is one of the gate drive technologies of liquid crystal panels. Its basic concept is to integrate the shift register unit of the liquid crystal panel on the array substrate to form a scanning drive for the liquid crystal panel. Compared with the traditional COF (ChipOnFlexiblePrintedCircuit) technology that fixes the chip on the flexible printed circuit and the COG (ChiponGlass) technology that fixes the chip on the glass, GOA technology not only saves costs, but also the LCD panel can achieve a beautiful design that is symmetrical on both sides. It also saves the bonding area of ​​the shift register unit and the fan-out wiring space to achieve a narrow frame design; at the same time, because the...

AI Technical Summary

Problems solved by technology

Since the logic power consumption of GOA mainly occurs when the Clock signal keeps charging and discharging the parasitic capacitance in its logic circuit, in order to reduce its logic power consumption, the main research direction in recent years is to reduce the parasitic capacitance in its logic circuit , however, since the GOA unit needs to charge and discharge the TFT capacitance of a row of pixels, the reduction of parasitic capacitance in the GOA logic circuit is limited

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