Integrated circuit pin testing device

Abstract

The invention discloses an integrated circuit pin testing device. The integrated circuit pin testing device comprises a main board and an expansion board. A first output end of a microcontroller arranged on the main board is electrically connected with an input end of a complex programmable logic device arranged on the expansion board and is used for transmitting a received test instruction to the complex programmable logic device. An output end of the complex programmable logic device is electrically connected with a first input end of a switch module. A first output end of the switch module is electrically connected with a tested pin of a tested integrated circuit. The complex programmable logic device controls a corresponding switch in the switch module to be switched on according to the test instruction. A second output end of the microcontroller is electrically connected with an input end of a constant-current source, and an output end of the constant-current source is electrically connected with a second input end of the switch module. The microcontroller controls the constant-current source to input corresponding test current to the tested pin after receiving the test instruction. By the integrated circuit pin testing device, the problems of large size and low portability due to structural complexity of an internal hardware circuit of a traditional OS (open / short) tester are effectively solved.

Description

technical field [0001] The invention relates to the field of integrated circuit testing, in particular to an integrated circuit pin testing device. Background technique [0002] Usually SOC (System on chip, system on chip or system-level chip) is in the process of client mass production (SMT / Assemble) due to ESD (Electrical Static Discharge, electrostatic discharge) / EOS (Electrical Over Stress, excessive electrical stress) reasons, making the chip appear pintoVCCshort (connection Power pin short circuit) and pintoGNDshort (ground pin short circuit) phenomenon, resulting in the chip not working properly. Since the occurrence of ESD / EOS is random and concealed, and the chip has a large number of pins, it is difficult to locate the short-circuited pins in a short time, so it is impossible to quickly locate the ESD / EOS scene. Therefore, it is necessary to use a third-party OS (Open / Short) tester (ie, a pin open / short tester) to test the pins of the chip. However, the tradition...

AI Technical Summary

Problems solved by technology

[0003] Based on this, it is necessary to provide an integrated circuit pin testing device for the problems that the traditional OS tester's internal hardware circuit structure is complex, resulting in high production costs, and it is not conducive to portability.

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