Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

IC pin testing device

An integrated circuit and test device technology, applied in the field of integrated circuit pin test devices, can solve the problems of high production cost, unfavorable portability, complex internal hardware circuit structure, etc., achieve volume reduction, facilitate portability, and solve the problem of large volume Effect

Active Publication Date: 2018-08-10
ALLWINNER TECH CO LTD
View PDF8 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] Based on this, it is necessary to provide an integrated circuit pin testing device for the problems that the traditional OS tester's internal hardware circuit structure is complex, resulting in high production costs, and it is not conducive to portability.

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • IC pin testing device
  • IC pin testing device
  • IC pin testing device

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0053] In order to make the technical solution of the present invention clearer, the present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0054] First of all, it should be noted that the O / S test refers to whether there is an open circuit or short circuit between the tested pin (Pin) and other Pins in verifying a failed IC (Integrated Circuit, integrated circuit). Wherein, in order to protect the pins in the IC, generally there will be a diode between Pin to VDD and Pin to GND in the IC during design. Therefore, by applying a constant current to the diode and testing the voltage drop across the diode, it can be determined whether the pin under test is an open circuit or a short circuit.

[0055] Based on the above test principles, in general, there are three test modes for O / S testing:

[0056] The first one is Pin to GND mode. In this test mode, the pin under test is connected to zero potential...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention discloses an integrated circuit pin testing device. The integrated circuit pin testing device comprises a main board and an expansion board. A first output end of a microcontroller arranged on the main board is electrically connected with an input end of a complex programmable logic device arranged on the expansion board and is used for transmitting a received test instruction to the complex programmable logic device. An output end of the complex programmable logic device is electrically connected with a first input end of a switch module. A first output end of the switch module is electrically connected with a tested pin of a tested integrated circuit. The complex programmable logic device controls a corresponding switch in the switch module to be switched on according to the test instruction. A second output end of the microcontroller is electrically connected with an input end of a constant-current source, and an output end of the constant-current source is electrically connected with a second input end of the switch module. The microcontroller controls the constant-current source to input corresponding test current to the tested pin after receiving the test instruction. By the integrated circuit pin testing device, the problems of large size and low portability due to structural complexity of an internal hardware circuit of a traditional OS (open / short) tester are effectively solved.

Description

technical field [0001] The invention relates to the field of integrated circuit testing, in particular to an integrated circuit pin testing device. Background technique [0002] Usually SOC (System on chip, system on chip or system-on-chip) is due to ESD (Electrical Static Discharge, electrostatic discharge) / EOS (Electrical OverStress, excessive electrical stress) during the mass production process (SMT / Assemble) of the client, so that The chip has pin to VCC short (short circuit of the pin connected to the power supply) and pinto GND short (short circuit of the ground pin), resulting in the chip not working properly. Since the occurrence of ESD / EOS is random and concealed, and the chip has a large number of pins, it is difficult to locate the short-circuited pins in a short time, so it is impossible to quickly locate the ESD / EOS scene. Therefore, it is necessary to use a third-party OS (Open / Short) tester (ie, a pin open / short tester) to test the pins of the chip. However...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Patents(China)
IPC IPC(8): G01R31/02G01R31/28
CPCG01R31/2851G01R31/50
Inventor 肖毅杨嘉毅高进
Owner ALLWINNER TECH CO LTD
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products