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Delay lock loop

A technology of delay-locked loop and delay unit, which is applied in the direction of output stability, automatic power control, pulse processing, etc., can solve the problems of frequency signal manufacturing process or temperature influence, integrated circuit cannot work normally, etc., to save circuit area and power consumption, large delay, precise delay effect

Active Publication Date: 2016-04-20
VIA ALLIANCE SEMICON CO LTD
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the frequency signal is easily affected by the manufacturing process or temperature
When the frequency signal deviates, it will cause the integrated circuit to fail to work normally

Method used

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Examples

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Embodiment Construction

[0022] Figure 1A It is an embodiment of the delay locked loop of the present invention. As shown in the figure, the delay locked loop 100A includes a delay unit 110 , a removal unit 120 , a phase detection unit 130 and a control unit 140 . The delay unit 110 has a delay coefficient, and delays the first frequency signal according to the delay coefficient to generate a second frequency signal. In this embodiment, the delay unit 110 for the input frequency signal CLK IN Delay to generate frequency signal CLK DL . The present invention does not limit the internal circuit structure of the delay unit 110 . Any circuit with a programmable delay function can be used as the delay unit 110 .

[0023] Frequency signal CLK DL with the input frequency signal CLK IN The delay time between is determined by the delay coefficient of the delay unit 110 . For example, when the delay coefficient is larger, the frequency signal CLK DL with the input frequency signal CLK IN The longer th...

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Abstract

The invention discloses a delay lock loop, comprising a selection unit, a delay unit and a phase detection unit; the selection unit receives a positive direction frequency signal and a negative position frequency signal and generates a first frequency signal and a second frequency signal according to an indication signal; the delay unit is coupled with the selection unit; the delay unit is equipped with a delay coefficient and delays the first frequency signal so as to generate a third frequency signal; the phase detection unit is coupled with the delay unit and the selection unit; the phase detection unit generates the indication signal according to the phase difference of the third frequency signal and the second frequency signal. The delay unit adjusts the delay coefficient according to the indication signal.

Description

technical field [0001] The invention relates to an electronic circuit, in particular to a delay locked loop. Background technique [0002] With the advancement of technology, more and more circuits are integrated into the same integrated circuit. Each circuit in an integrated circuit operates according to a frequency signal. However, the frequency signal is easily affected by the manufacturing process or temperature. When the frequency signal deviates, it will cause the integrated circuit to fail to work normally. Contents of the invention [0003] In view of this, the object of the present invention is to provide a delay locked loop, comprising: a selection unit, a delay unit, and a phase detection unit. The selection unit receives the forward frequency signal and the reverse frequency signal, and generates a first frequency signal and a second frequency signal according to the indication signal. A delay unit is coupled to the selection unit. The delay unit has a del...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03L7/081H03L7/08
CPCH03L7/0805H03L7/0812H03L1/02H03K5/134H03K2005/00019
Inventor 司强姜凡
Owner VIA ALLIANCE SEMICON CO LTD
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