A connection device between jtag interface and internal user logic

Abstract

The invention provides a JTAG interface and internal user logic connecting device. The JTAG interface and internal user logic connecting device comprises a concentrator module, a JTAG interface is connected with the concentrator module through a JTAG bus, the concentrator module is connected with multiple internal user logics through a concentrator interface bus, and the multiple internal user logics select communication through chip select signals corresponding to the internal user logics. The JTAG interface and internal user logic connecting device is only provided with one bus, wiring resources of chips are decreased, and the timing sequence performance is improved.

Description

technical field [0001] The invention relates to the technical field of JTAG, in particular to a connection device between a JTAG interface and user logic inside a chip. Background technique [0002] In recent years, with the development of microprocessor technology, more and more processors and logic devices use the JTAG (Joint Test Action Group) interface as an intermediary between their cores and PCs. The JTAG interface is a boundary-scan protocol specified in IEEE1149.1. The JTAG protocol is often used for internal testing of chips. Most advanced devices now support the JTAG protocol, such as ARM, DSP, and FPGA (Field-Programmable Gate Array) devices. In the FPGA, the JTAG interface can be used as a part of the configuration function module. The PC can program and configure the FPGA through the JTAG interface, and can also access the internal user logic (User APP IP) through the JTAG interface. User APP IP can be debugging tools, such as embedded Debugcore logic analyzer...

AI Technical Summary

Problems solved by technology

[0004] In the process of realizing the present invention, the inventor finds that there are at least the following technical problems in the prior art: the controller processing module has too many interface connections to the internal user logic, which will take up too many FPGA wiring resources. As a core processing module, it takes up more logic resources, which makes the timing performance of the system not high.

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