Charge pump circuit for low power supply voltage condition

Abstract

The invention discloses a charge pump circuit for a low power supply voltage condition. A plurality of levels of circuits are cascaded to form the charge pump circuit; each level of circuit includes two resistors, two capacitors and two PMOS transistors, wherein one end of the first resistor is connected with one end of the first capacitor, the drain of the first PMOS transistor is connected with the gate of the second PMOS transistor, and one end of the second resistor is connected with one end of the second capacitor, the drain of the second PMOS transistor is connected with the gate of the first PMOS transistor. The charge pump circuit of the invention can work stably and reliably under the low power supply voltage condition.

Description

technical field [0001] The invention relates to a charge pump circuit. In particular, it relates to a charge pump circuit for low supply voltage conditions. Background technique [0002] With the continuous improvement of semiconductor manufacturing technology and integrated circuit design capabilities, people have been able to integrate processors, memory, analog circuits, interface logic and even radio frequency circuits into one chip, which is the System-on-Chip (System-on-Chip, SoC). As the data throughput continues to rise and the system requires low power consumption, the SoC core voltage (corevdd) is gradually reduced. Currently, the core voltage of an SoC system is generally below 1.8V, and it is foreseeable that it will be further reduced to 1.5V or even 1.2V in the near future. This brings great challenges to the design of analog circuits, especially circuits that are sensitive to power supply voltage, such as charge pump circuits. In many systems that use char...

AI Technical Summary

Problems solved by technology

In many systems using charge pumps, the dual power supply mode has to be used to solve the above contradictions. However, the dual power supply makes the power system of the chip more complicated, and the power network design, device isolation and ESD protection design are more difficult.

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