FPGA-based shakeless drive control system of stepping motor and control method based on same

A stepping motor, drive control technology, applied in the control system, motor generator control, electrical components, etc., can solve the problems of complex electrical system structure, poor drive timing accuracy, and insufficient external communication interfaces, so as to improve anti-interference performance, reduce the complexity of the electrical structure, and achieve the effect of jitter-free driving

Active Publication Date: 2016-05-11
HARBIN INST OF TECH
5 Cites 4 Cited by

AI-Extracted Technical Summary

Problems solved by technology

[0003] In order to solve the problems that the traditional stepper motor control system cannot avoid the poor accuracy of drive timing control, the lack of rich e...
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Abstract

The invention provides an FPGA-based shakeless drive control system of a stepping motor and a control method based on the system, relating to the field of stepping motor control and solving the problem that a traditional stepping motor control system cannot avoid poor timing control accuracy during driving, shortage of external communication interfaces and structure complexity of an electric system. According to the system disclosed by the invention, an upper computer carries out data interaction with an FPGA controller through a serial communication bus; the FPGA controller outputs a pulse signal, a direction signal, an enable signal and a mode signal to a digital signal isolation module; a control signal output end of the digital signal isolation module is connected with a control signal input end of a stepping motor drive module; the stepping motor drive module drives an external motor; a power isolation module is respectively connected with the FPGA controller, the digital signal isolation module and the stepping motor drive module. Through using FPGA and integrating a stepping motor power drive chip, the complexity of the electric structure of the stepping motor drive control system can be reduced largely and moreover multi-communication-mode expansion capability is also considered.

Application Domain

Dynamo-electric converter control

Technology Topic

VIT signalsMotor drive +9

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  • FPGA-based shakeless drive control system of stepping motor and control method based on same
  • FPGA-based shakeless drive control system of stepping motor and control method based on same

Examples

  • Experimental program(9)

Example Embodiment

[0024] Specific implementation mode one, combination figure 1 To illustrate this specific embodiment, an FPGA-based stepper motor jitter-free drive control system described in this specific embodiment includes a host computer 1, an FPGA controller 2, a power isolation module 3, a digital signal isolation module 4, and a stepper motor Drive module 5, the host computer 1 realizes data interaction with FPGA controller 2 through serial communication bus, FPGA controller 2 outputs pulse signal PULUp, direction signal DIR, enable signal ENA and mode signal M1 to digital signal isolation module 4 , M2 and M3, the control signal output end of the digital signal isolation module 4 is connected to the control signal input end of the stepping motor drive module 5. The stepping motor drive module 5 drives the external motor, and the power isolation module 3 is connected to the FPGA controller 2 respectively. The digital signal isolation module 4 is connected to the stepping motor drive module 5.

Example Embodiment

[0025] Specific implementation mode two, combination figure 1 To illustrate this specific embodiment, the difference between this specific embodiment and the FPGA-based stepper motor jitter-free drive control system described in specific embodiment 1 is that the FPGA controller 2 includes a serial communication control interface module 6, The Nios soft processing module 7, the stepping motor drive control interface module 8 and the timer 9. The serial communication control interface module 6 realizes data interaction with the host computer 1 through the serial communication bus, and the Nios soft processing module 7 through the Avalon bus respectively Realize data interaction with serial communication control interface module 6, stepper motor drive control interface module 8 and timer 9.

Example Embodiment

[0026] Specific implementation mode three, combination figure 2 To illustrate this specific embodiment, the difference between this specific embodiment and the FPGA-based jitter-free drive control system of a stepper motor described in the first embodiment is that the stepper motor drive control interface module 8 includes:
[0027] Control parameter writing process module for controlling parameter writing process;
[0028] A control parameter update process module for controlling the parameter update process;
[0029] Control output process module for controlling output process;
[0030] The control mode register ControlMode_reg used to receive the signal sent by the control parameter writing process module and store the signal;
[0031] Driving timing counter TimerCounter_reg for driving timing counting;
[0032] The single pulse control period parameter register ControlPeriod_reg used to receive the signal sent by the control parameter update process module and store the signal;
[0033] The expected single pulse period parameter register NewPeriod_reg of the current communication period for storing the expected single pulse period parameter of the current communication period;
[0034] The expected single-pulse period parameter register HistoryPeriod_reg of the last communication period used to store the expected single-pulse period parameter of the last communication period;
[0035] The control parameter update process module startup module StartUpdataProcess_bit used to control the startup of the parameter update process module;
[0036] The control parameter update process module stop module EndUpdataProcess_bit used to control the parameter update process module stop.

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Description & Claims & Application Information

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