Thin film transistor and manufacturing method, array substrate and display device

Abstract

The invention discloses a thin film transistor and a manufacturing method, an array substrate and a display device, and belongs to the field of display processing technology. The thin film transistor comprises a first etching barrier layer, a second etching barrier layer, a source, a drain, an insulating layer and an active layer; the insulating layer is arranged on the active layer, the first etching barrier layer and the second etching barrier layer, and the insulating layer is provided with a first contact hole and a second contact hole; the source is electrically connected with the active layer via the first contact hole, and the drain is electrically connected with the active layer via the second contact hole; the first etching barrier layer is positioned between the active layer and the source; and the second etching barrier layer is positioned between the active layer and the drain. When the insulating layer is etched with the contact holes, the contact holes can be directly etched onto the first etching barrier layer and the second etching barrier layer to prevent under-etching, and the first etching barrier layer and the second etching barrier layer block the active layer to prevent the active layer from being etched and prevent over-etching, so that the yield of the thin film transistor is improved.

Description

technical field [0001] The invention relates to the field of display processing, in particular to a thin film transistor, a manufacturing method, an array substrate, and a display device. Background technique [0002] Thin-film transistors are used to make displays with high-end display effects. The light emitted by each pixel on the display is driven by an integrated thin-film transistor behind it. [0003] At present, the manufacturing method of a thin film transistor includes: forming an active layer, the active layer includes a source doped region and a drain doped region, depositing an insulating layer on the active layer, respectively insulating the doped source region layer and the insulating layer above the doped drain region are etched to expose the doped source region and the doped drain region and form two contact holes, and a source and drain metal layer is deposited on the insulating layer, which is formed after the patterning process source and drain. [000...

AI Technical Summary

Problems solved by technology

[0005] At present, when etching a contact hole on an insulating layer, due to the difficulty in mastering the etching process, the contact hole is often under-etched or over-etched, which will have a negative impact on the thin film transistor and reduce the yield of the thin film transistor.

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