non-volatile memory

Abstract

The invention discloses a non-volatile memory. The non-volatile memory is arranged on a substrate comprising a peripheral circuit area and a memory cell area. The non-volatile memory comprises a floating gate transistor, a transistor, a self-aligning barrier layer, a stretching layer and a contact etching termination layer. The floating gate transistor is arranged in the memory cell area. The transistor is arranged in the peripheral circuit area. The self-aligning barrier layer is arranged on a floating gate of the floating gate transistor. The stretching layer is arranged on the floating gate. The contact etching termination layer covers the whole transistor.

Description

technical field [0001] The present invention relates to a semiconductor element, and more particularly to a non-volatile memory. Background technique [0002] When the semiconductor enters the deep sub-micron (Deep Sub-Micron) manufacturing process, the size of the element is gradually reduced. For the memory element, it means that the size of the memory cell is getting smaller and smaller. On the other hand, as information electronic products (such as computers, mobile phones, digital cameras or personal digital assistants (PDA)) need to process and store more data, the memory capacity required in these information electronic products It's getting bigger and bigger. For such a situation where the size is reduced but the memory capacity needs to be increased, how to manufacture memory elements with reduced size, high integration, and quality is a common goal of the industry. [0003] The non-volatile memory element has become a memory element widely used in personal comput...

AI Technical Summary

Problems solved by technology

The contact etch stop layer is made of silicon nitride formed by plasma-enhanced chemical vapor deposition, which will cause the floating gate transistor to have low on-current (Low On Current) and poor retention performance.

However, if the material of the contact etch stop layer is changed, the performance of the transistors in the peripheral circuit area will be affected.

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