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High-voltage flip chip structure and preparation method thereof

A flip-chip, high-voltage technology, which is applied in the direction of electrical components, circuits, semiconductor devices, etc., can solve the problems that affect the reliability of LED chips, the temperature of LED chips rises, and the heat conduction and stability of LED chips have not been solved. Achieve the effects of avoiding waste of raw materials, increasing pad area, and reducing precision requirements

Active Publication Date: 2016-06-01
SHANDONG INSPUR HUAGUANG OPTOELECTRONICS
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  • Application Information

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Problems solved by technology

However, the flip-chip high-voltage chip epitaxial wafer still uses traditional metal bumps to conduct electricity. When working at a high current, the heat generated by welding or the heat generated by the LED chip will increase the temperature of the LED chip and affect the reliability of the LED chip. , the heat conduction and stability problems of LED chips have not been resolved

Method used

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  • High-voltage flip chip structure and preparation method thereof
  • High-voltage flip chip structure and preparation method thereof
  • High-voltage flip chip structure and preparation method thereof

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Embodiment Construction

[0043] The high-voltage flip-chip structure of the present invention has a structure such as image 3 As shown, a substrate 1, an N-type GaN layer 2, a quantum well active region 3, a P-type GaN layer 4, a light reflection layer 10 and a TiW barrier layer 20 are sequentially arranged from top to bottom, and the P-type GaN layer 4 is provided with There is a P electrode 5 , an N electrode 7 is arranged on the N-type GaN layer 2 , and a TiW barrier layer 20 is arranged on the light reflection layer 10 other than the P electrode 5 and the N electrode 7 . SiO is provided on the TiW barrier layer 20 2insulating layer 15. The bottoms of the P electrode 5 and the N electrode 7 are provided with an electrode metal layer 16, the electrode metal layer at the bottom of the P electrode 5 is provided with a P pole pad 18, and the electrode metal layer at the bottom of the N electrode 7 is provided with an N pole pad 19, Between the P pole pad 18 and the N pole pad 19, SiO 2 insulating l...

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Abstract

The invention relates to a high-voltage flip chip structure and a preparation method thereof. A substrate, an N type GaN layer, a quantum well active region, a P type GaN layer, a light reflecting layer and a metal barrier layer are arranged successively at the chip structure from top to bottom. A P electrode is arranged on the P type GaN layer and an N electrode is arranged on the N type GaN layer. A TiW barrier layer is arranged at the part, except the P electrode and the N electrode, of the light reflecting layer; an insulating layer is arranged on the TiW barrier layer; a P pole welding plate and an N pole welding plate are arranged at the bottoms of the P electrode and the N electrode by electrode metal films; and an inter-welding-plate insulating layer is arranged between the P pole welding plate and the N pole welding plate. Besides, the preparation method includes: preparing an epitaxial wafer, carrying out evaporation on a light reflection layer; depositing a metal barrier layer; plating an electrode metal film; cutting an isolation groove; depositing insulating layer, plating an FC metal film; manufacturing an inter-welding plate insulating layer; and carrying out cutting to obtain a needed high-voltage flip chip. Therefore, high-voltage driving is realized; metal diffusion of the light reflecting layer is prevented; the insulation performance is good; and the stability and reliability of the chip and the device are improved.

Description

technical field [0001] The invention relates to a high-voltage flip-chip structure and a preparation method thereof, and belongs to the technical field of LED (light-emitting diode) chip preparation. Background technique [0002] With the increasing demand for personalization and lightness of electronic products worldwide, packaging technology has advanced to CSP (ChipSizePackage). It reduces the size of the chip package outline, so that the size of the package can be as large as the size of the bare chip. The CSP package not only meets the ever-increasing needs of chip I / O pins, but also has a very small ratio between the chip area and the package area, which greatly shortens the delay time. Therefore, the flip-chip manufacturing process has attracted the attention of the industry, and many people in the industry even predict that this process will become the mainstream technology of LED packaging in the future. [0003] LED front-mount chip is the earliest chip structure...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L33/58H01L33/60H01L33/62H01L33/00
CPCH01L33/58H01L33/60H01L33/62H01L2933/0058H01L2933/0066
Inventor 曹志芳夏伟徐现刚
Owner SHANDONG INSPUR HUAGUANG OPTOELECTRONICS
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