Artificial neural network-based out-of-order processor Cache memory access performance evaluation method

Abstract

The invention discloses an artificial neural network-based out-of-order processor Cache memory access performance evaluation method, and aims at solving the problem that the memory access instructions are executed out of order so that the stacking distance distribution extracted by utilizing a binary execution tool during the prediction of LRU-Cache memory access behaviors is low in precision. The method comprises the following steps: combining a read-black tree and a hash table; designing a Cache group association architecture-based stacking distance extraction algorithm; respectively calculating a memory access sequence and the stacking distance distribution executed out of order; fitting the stacking distance distribution executed according to the memory access sequence and a memory access missing number by utilizing a BP neural network; and importing the stacking distance distributed extracted on the basis of the binary execution tool into the trained neural network so as to predict the Cache memory access behaviors with high precision. According to the method disclosed in the invention, the artificial neural network is adopted, so that the problem that the stacking distance distribution extracted by utilizing the binary execution tool during the prediction of the Cache memory access behaviors is low in precision is effectively solved.

Description

technical field [0001] The invention relates to a method for evaluating memory access performance of an out-of-order processor Cache based on an artificial neural network, and belongs to the field of software-hardware collaborative design. Background technique [0002] Pre-silicon architecture evaluation and design space exploration based on hardware behavior modeling can provide chip design guidance and reduce chip design iteration cycles. Cache, as an on-chip cache, has a great impact on processor memory access performance. Missing access will cause bubbles in the processor pipeline or cause pipeline blockage, reducing processor computing performance. In addition, Cache occupies a large amount of chip area and consumes a lot of power consumption, so the processor design needs to design the organizational structure of Cache more reasonably. [0003] In recent years, the research on Cache memory access performance can be divided into two directions. One is to reduce the num...

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Problems solved by technology

[0007] Purpose of the invention: In order to overcome the deficiencies in the prior art, the present invention provides a method for evaluating memory access performance of out-of-order processors based on artificial neural networks, which solves the problem of using binary execution tools to extract stack distance distributions in predicting Cache The problem of low precision in memory access behavior

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