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Power good signal output method and device

A signal output and signal technology, which is applied in the field of good power signal output methods and devices, can solve problems such as affecting the accuracy of power good state judgment, affecting the overall performance of display driver chips, and protecting circuit misoperations, so as to solve competition and risk-taking problems. , the effect of eliminating burr phenomenon, zero power consumption static current

Active Publication Date: 2021-02-26
GALAXYCORE SHANGHAI
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0012] It can be seen that due to the competition and risk problems caused by the different delays of the enable switch and the judgment module, there will be glitches in the actual response output (t1-t2 stage), which will affect the judgment accuracy of the power supply status, and will cause subsequent protection circuits. Misoperation, which will affect the overall performance of the display driver chip

Method used

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  • Power good signal output method and device

Examples

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Embodiment 1

[0078] FIG. 7(A) shows the circuit diagram of the power good signal output subunit of Embodiment 1 of the present invention, and FIG. 7(B) shows the effect diagram of the power good signal output subunit of Embodiment 1 of the present invention.

[0079] As shown in Figure 7(A), the power good signal output subunit of the present invention includes a voltage divider module 221 with an enable switch 224, a forward judgment module 222 and a trigger 223, wherein the enable switch 224 is close to the ground wire terminal (GND terminal).

[0080] Wherein, the voltage dividing module 221 converts the input power supply voltage VDDN into a detection divided voltage VDDN' that can be judged by dividing the voltage by resistors. Since the voltage divider module 221 is provided with an enable switch 224 responsive to the enable signal EN, the static power consumption of the voltage divider resistor string can be zero in deep sleep or shutdown mode through the control of the enable signa...

Embodiment 2

[0089] FIG. 8(A) shows the circuit diagram of the power good signal output subunit of the second embodiment of the present invention, and FIG. 8(B) shows the effect diagram of the power good signal output subunit of the second embodiment of the present invention.

[0090] As shown in FIG. 8(A), the power good signal output subunit of the present invention includes a voltage divider module 321 with an enable switch 324, a forward judgment module 322 and a trigger 323, wherein the enable switch 324 is close to the power supply voltage end (VDDN end).

[0091] Wherein, the voltage dividing module 321 converts the input power supply voltage VDDN into a detection divided voltage VDDN' that can be judged by dividing the voltage by resistors. Since the voltage divider module 321 is provided with an enable switch 324 that responds to the enable signal EN, the static power consumption of the voltage divider resistor string can be zero in deep sleep or shutdown mode through the control ...

Embodiment 3

[0100] FIG. 9(A) shows the circuit diagram of the power good signal output subunit of the third embodiment of the present invention, and FIG. 9(B) shows the effect diagram of the power good signal output subunit of the third embodiment of the present invention.

[0101] As shown in Figure 9(A), the power good signal output subunit of the present invention includes a voltage divider module 421 with an enable switch 424, a reverse judgment module 422 and a trigger 423, wherein the enable switch 424 is close to the power supply voltage end (VDDN end).

[0102] Wherein, the voltage dividing module 421 converts the input power supply voltage VDDN into a detection divided voltage VDDN' that can be judged by dividing the voltage by resistors. Since the enable switch 424 is provided in the voltage divider module 421 in response to the enable signal EN, the static power consumption of the voltage divider resistor string can be zero in deep sleep or shutdown mode through the control of ...

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Abstract

The present invention provides a method and device for outputting a power good signal. The device includes: a voltage dividing module with an enabling switch, which is used to convert the input power supply voltage into a detection divided voltage that can be judged. The enabling switch In response to the enable signal, the power supply voltage is a positive value or a negative value; a forward judgment module or a reverse judgment module is used to judge the detection divided voltage and output a flag signal; a trigger is used to process the enable Signal and flag signal, output power good signal. The present invention uses a trigger to process the enable signal and the flag signal to output the power good signal, which can not only realize the static current of zero power consumption in the deep sleep or shutdown mode, but also solve the competition caused by the different delays of the enable switch and the judgment module And risky problems, eliminate the glitch phenomenon in the actual response output, improve the judgment accuracy of the good state of the power supply, and improve the overall performance of the display driver chip.

Description

technical field [0001] The invention relates to the field of integrated circuits, in particular to a power good signal output method and device. Background technique [0002] With the increasing popularity of smart phones, people have higher and higher requirements for the display effect of mobile smart terminals, and the display effect of wide screen and high resolution with high performance has become the mainstream. Therefore, more and more challenges are raised to the functions and performance of the display driver chip of the handheld device. [0003] The charge pump in the multi-output power management unit, which is very important in the display driver chip, provides positive and negative bias voltages for the liquid crystal. During the process of power-on or power-off, the charge pump module needs to be charged and discharged for several clock cycles to achieve Therefore, it is particularly important to detect the states of the multiple positive and negative output ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G09G3/20
CPCG09G3/2077
Inventor 张科王富中丁启源
Owner GALAXYCORE SHANGHAI
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