SHEPWM (selective harmonic elimination pulse width modulation) control circuit, double-T-type three-level SHEPWM inverter parallel system and method therefor
A three-level inverter, control circuit technology, applied in electrical components, AC power input into DC power output, output power conversion devices and other directions, can solve the hardware mismatch dead time control algorithm execution time, influence IGBT switch tube life, grid-connected current distortion and other issues, to achieve the effect of solving the problem of circulating current suppression, low harmonic content, and solving the problem of midpoint voltage balance
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[0069] Below in conjunction with accompanying drawing and embodiment the present invention will be further described:
[0070] The topology diagram of the three-level inverter parallel system is as follows: figure 1 As shown, the two inverters share the AC and DC busbars, P and N are the positive and negative busbars of the parallel system; A, B, and C are the three-phase grid connection points of the parallel system; aj, bj, and cj are the AC outputs of the inverters end, C j1 、C j2 It is two capacitors connected in parallel with the DC side, and the midpoint is Z j , the filter adopts LC filter, and the filter inductance is L i , the filter capacitor is C mj , the zero sequence current is i zj , i mj is the m-phase output current of the j-th inverter, m=a, b, c, j=1, 2, 3; i A i B i C is the grid-connected current of the system.
[0071] as figure 2 The single inverter structure shown illustrates the inverter control strategy. Two capacitors C are connected in s...
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