Semiconductor device and method of manufacturing the same

Abstract

Provided is a semiconductor device. The semiconductor device comprises a first device layer and a second device layer positioned above the first device layer, the first device layer comprises a plurality of first fin structures on a substrate and a first grid electrode stacking structure across the plurality of first fins structures, the second device layer comprises a plurality of second fin structures and a second grid electrode stacking structure across the plurality of second fin structures, and each second fin of the plurality of second fin structures is positioned between each two adjacent first fins of the plurality of first fin structures. According to the semiconductor device and a manufacturing method thereof, the top device layer containing a plurality of fins and grids is formed above areas between the plurality of fins of the bottom device layer, the areas between the fins of the FinFET device can be reasonably used, the driving capability of the device is improved, the increase of the chip area is avoided, and the overall performance of the device is effectively enhanced.

Description

technical field [0001] The invention relates to a semiconductor device and a manufacturing method thereof, in particular to a multilayer FinFET including a vertically stacked 3D structure and a manufacturing method thereof. Background technique [0002] Three-dimensional multi-gate devices such as fin field-effect transistors (FinFETs) and tri-gate (tri-gate) devices are among the most promising new device technologies as device dimensions scale down to 22nm technology and below. The gate control ability suppresses leakage and short channel effects. [0003] For the traditional process, the gate patterning and contact formation of CMOS devices including FinFET and tri-gate devices are performed through the following steps in order to realize isolated functional devices: [0004] 1. Using line-and-cut (line-and-cut) dual lithography patterning technology and subsequent etching of the gate stack to pattern the gate; [0005] 2. Use uniform feature size and pitch (pitch) to p...

AI Technical Summary

Problems solved by technology

The pitch between the fin and the gate electrode of FinFET 3D devices is getting smaller and smaller, making the patterned etching and filling process more and more difficult

Therefore, the integration of devices composed of multiple FinFET arrays arranged in a traditional two-dimensional array is limited by the process used to form electrical contacts and electrical interconnections.

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