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Modified Booth coding multiplier based on modified partial product array

A technology of multipliers and arrays, applied in the design field of high-speed parallel multipliers, can solve the problems of multiplier delay and area increase

Active Publication Date: 2016-07-06
NANJING UNIV OF AERONAUTICS & ASTRONAUTICS
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Problems solved by technology

[0004] In ordinary n-bit multiplication, the partial product is obtained by multiplying each bit of the multiplier with the multiplicand. This simple multiplication method will generate n rows of partial products. As the number of bits n increases, the delay of the multiplier Time and area also increase

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  • Modified Booth coding multiplier based on modified partial product array
  • Modified Booth coding multiplier based on modified partial product array
  • Modified Booth coding multiplier based on modified partial product array

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Embodiment Construction

[0024]The present invention will be further described below in conjunction with the accompanying drawings.

[0025] The overall structure of the n-bit high-speed parallel multiplier with improved partial product array structure is shown in the attached image 3 shown. in the attached image 3 In , the modified Booth encoder is used to encode the n-bit multiplicand A and multiplier B, and the n / 2 row of partial products and an extra row of error correction words are generated through the codec circuit. The schematic diagram of the modified Booth codec circuit structure is attached Figure 4 shown. The present invention eliminates an extra line of error correction words through correction of error correction words while Booth encoding is performed. The improved partial product array produces two rows of 2n-bit partial products after 4:2 compression or 3:2 compression of the Wallace tree structure, which are added by a 2n-bit look-ahead adder to obtain a 2n-bit product.

[00...

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Abstract

The present invention provides a circuit structure of a modified Booth multiplier for modifying the number of partial product arrays. Targeted at partial products generated by a modified Booth coding, the circuit structure performs a summation operation on an extra line of error correction words and a first line as well as a final line of partial products, so as to transfer to the highest position through the shortest path, so that the extra line of error correction words are eliminated, first-level partial product compression is reduced, and the speed of a multiplier is effectively improved.

Description

technical field [0001] The invention belongs to the field of digital integrated circuits, in particular to the design of a high-speed parallel multiplier. Background technique [0002] Since the invention of the transistor in the 20th century, the microelectronic integrated circuit industry has been following Moore's law to develop rapidly. By the 21st century, the information industry has become the standard for measuring the country's independent innovation strength and comprehensive strength. As the technology of integrated circuits gradually matures, and the level of deep submicron technology is getting higher and higher, how to realize the microprocessor with smaller size, faster speed and lower power consumption has become the research goal and research direction of researchers. [0003] As a very important computing component in digital signal processing, filters, processors and other devices, the multiplier plays an important role in the processing of data, images, ...

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Application Information

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IPC IPC(8): G06F7/53
CPCG06F7/5312
Inventor 崔晓平董文雯王书敏张柳
Owner NANJING UNIV OF AERONAUTICS & ASTRONAUTICS
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