Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

SAT automatic integrated solver based on FPGA

A solver and automatic technology, applied in the direction of instruments, memory systems, complex mathematical operations, etc., can solve problems such as poor versatility and no practical value, and achieve the effects of saving time, improving test efficiency, and powerful functions

Active Publication Date: 2016-07-06
何安平
View PDF2 Cites 4 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In this method, each instance corresponds to a different hardware structure, and each chip can only solve certain instances, which has poor versatility and almost no practical value.

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • SAT automatic integrated solver based on FPGA
  • SAT automatic integrated solver based on FPGA
  • SAT automatic integrated solver based on FPGA

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0044] First, the translator written in C++ automatically translates the CNF formula into verilog language, that is, compiles the CNF into a gate-level circuit form, and then simulates the gate-level circuit through Questasim software to check whether the simulation is the same as the theoretical logic, and then passes Precision to the The circuit is optimized and synthesized, and finally the QuartusII software integrated in Precision is called to configure the pins. Finally, the integrated file is downloaded to the FPGA circuit board and solidified as hardware logic to form a Clause logic calculation module of CNF, which is searched for values ​​by exhaustive method. , to verify the satisfiability of the example, connect the output to the pin of the buzzer or LED light, if the output is high, the buzzer sounds or the LED light is on, it is intuitively proved that this CNF can be satisfied, Otherwise the proof is unsatisfactory. Optimize and synthesize the circuit through Prec...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention provides an SAT automatic integrated solver based on FPGA, which effectively judges that whether CNF can be met. Firstly, the CNF is automatically translated to the verilog language by a C++ translator, i.e. the conjunctive normal form is converted to the gate level circuit form; the gate level circuit is simulated via Questasim software, whether the simulation is the same with a theoretical logic is checked, then the circuit is optimized and synthesized via Precision software, at last QuartusII software integrated into the Precision software is called to perform pin configuration, thus the integrated file is finally downloaded onto the FPGA circuit board to be cured into the hardware logic for verification; and the cured FPGA chip is embedded into the embedded chip, the automation of the whole process for generating a file calling command is achieved through combined programming of the Tcl scripting language and high-level language C++, and thereby whether the CNF can be met is rapidly judged. The hardware compiling configuration time is added, and thereby the time of the whole process can be more accurately computed compared with other hardware SAT solvers.

Description

1. Technical field: [0001] The invention belongs to the field of special-purpose FPGA chip design. 2. Background technology: [0002] SAT (satisfiability problem), that is, (Boolean) satisfiability problem is one of the core problems of computer theory and application, and it is also the first proven NP problem. A variety of practical problems, such as automatic switching technology of program-controlled telephones, robot action planning, etc., can be transformed into SAT problems to solve. At present, SAT has been applied in the fields of computer system structure design, logical reasoning, model testing, integrated circuit design and artificial intelligence, especially in the field of integrated circuit design verification, SAT has extremely extensive and in-depth applications. [0003] With the development of the electronics industry in recent decades, integrated circuit systems have become increasingly complex and large-scale integrated, the design complexity has become...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Applications(China)
IPC IPC(8): G06F17/15G06F9/45
Inventor 何安平吴尽昭宋晓宇毛乐乐熊菊霞
Owner 何安平
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products