39 results about "Conjunctive normal form" patented technology

An improved normalization methodology enabling better optimization of SQL queries is described. The normalization methodology effectively handles three-valued SQL search conditions and operates in reduced memory environments. A query is examined and selectively normalized by examining each segment of the query to determine whether it is advantageous to fully convert that segment to conjunctive normal form (CNF). If full conversion of the segment to CNF is not advantageous, then only the useful conjunctive conditions (prime implicates) that can be derived from the original input are saved. These useful conjuncts (prime implicates) are unioned with the original statement, resulting in a search condition that is semantically equivalent to the original expression, but that can be better exploited by a query optimizer. This enables better optimization of the original query without the system overhead that would result from full normalization of the query.

A method for Boolean Satisfiability (SAT). The method comprises using a variable decision heuristic in a SAT algorithm and pruning the search space of SAT using said decision heuristic. The decision heuristic is based on partitioning a conjunctive normal form (CNF) of a Boolean formula corresponding to the SAT and the partitioning is induced by a separator set. An image computaion method that uses the disclosed method for solving the SAT.

This disclosure teaches a method of Boolean satisfiability checking (SAT) for a circuit. The method comprises identifying inactive clauses in the conjunctive normal form (CNF) of the circuit and removing the inactive clauses from the CNF.

Provided is a totally new formal verification algorithm aiming at an arithmetic circuit. One example embodiment provides a new formal method which couples (combines) a satisfiability (SAT) solver and a unique Reverse Engineering (RE) method which makes use the arithmetic logical circuit structure properties (e.g. 1-bit adder structure, Carry tree structure) to achieve the algorithm for arithmetic circuits regardless of its size. The example embodiment provides basic through of how to optimize the operational complexity of a conventional arithmetic circuit verification method. The basic through is shown as followed: assuming that there are two arithmetic circuits f and g; conducting equivalence checking of the two arithmetic circuits by firstly generating a conjunctive normal form (CNF) encoding; and determining whether the encoding of the two arithmetic circuits is equal through a satisfiability (SAT) tool. If the structural difference between f and g is minimized as far as possible before generating a conjunctive normal form (CNF) encoding, the arithmetic circuit verification is completed in polynomial time rather than in exponential time.

One embodiment provides a system that facilitates a flexible strategy for matching content objects and interests. During operation, the system receives, by a computing device, an interest which includes a set of attributes, wherein a respective attribute has one or more values. In response to not obtaining a matching entry for the interest in a pending interest table, the system adds to the pending interest table a first entry which indicates the interest based on the attributes and their values. The system determines whether a received content object satisfies the interest indicated in the first entry based on the attributes of the first entry and attributes of the content object. In response to determining that the content object satisfies the interest, the system forwards the content object, thereby facilitating a flexible strategy for matching content objects to interests.

One embodiment of the present invention provides a system for forwarding packets with hierarchically structured variable-length identifiers (HSVLIs) in a content-centric network (CCN). During operation, the system receives a packet with an HSVLI and determines, based on the HSVLI, a plurality of ports to which the packet should be forwarded. The plurality of ports include a set of individual port groups, and a respective port group includes one or more individual physical ports. The system derives a forwarding strategy based on the set of individual port groups and the one or more individual physical ports. The forwarding strategy is expressed as a formula in conjunctive normal form that indicates a logical conjunction among the set of port groups and a logical disjunction among the one or more individual physical ports. The system then forwards the packet using the derived forwarding strategy.

A method for analyzing system-problems, comprising the steps of: accepting from a user an input describing a system having a problem; parsing the user input to create a boolean representation of the system, the boolean representation comprising a series of equations; determining that the boolean representation comprises an unsatisfiable series of equations; for each equation in the series of equations, performing the steps of: creating a modified series of equations by removing the equation from the series of equations; and determining if the modified series of equations is satisfiable, and, if the modified series of equations is satisfiable, deriving a solution wording from the removed equation.

An apparatus includes a state machine engine. The state machine engine may also include an automaton, whereby the automaton is configured to analyze data from a beginning of an input data stream until a point when an end of data signal is seen. The automaton may further be configured to report an event representative of a satisfaction of a Boolean clause of a conjunctive normal form (CNF) Boolean expression representative of a Boolean Satisfiability problem (SAT) by a portion of the input data stream.

The invention provides an SAT automatic integrated solver based on FPGA, which effectively judges that whether CNF can be met. Firstly, the CNF is automatically translated to the verilog language by a C++ translator, i.e. the conjunctive normal form is converted to the gate level circuit form; the gate level circuit is simulated via Questasim software, whether the simulation is the same with a theoretical logic is checked, then the circuit is optimized and synthesized via Precision software, at last QuartusII software integrated into the Precision software is called to perform pin configuration, thus the integrated file is finally downloaded onto the FPGA circuit board to be cured into the hardware logic for verification; and the cured FPGA chip is embedded into the embedded chip, the automation of the whole process for generating a file calling command is achieved through combined programming of the Tcl scripting language and high-level language C++, and thereby whether the CNF can be met is rapidly judged. The hardware compiling configuration time is added, and thereby the time of the whole process can be more accurately computed compared with other hardware SAT solvers.

A processor including a Boolean logic unit, wherein the Boolean logic unit is operable for performing the short-circuit evaluation of Conjunctive Normal Form Boolean expressions / operations, a plurality of input / output interfaces, wherein the plurality of input / output interfaces are operable for receiving a plurality of compiled Boolean expressions / operations and transmitting a plurality of compiled results, and a plurality of registers. An associated processing method including starting an operation related to a Conjunctive Normal Form Boolean expression, wherein the Boolean expression comprises a conjunct, evaluating the conjunct, and selectively short-circuiting a portion of the Boolean expression.

A novel method for optimizing the implementation of clock gating logic in digital circuits utilizing clock gating. The method over-approximates the clock gating function by removing the variable with the least influence on the resulting approximation function. Approximations of clock gating functions expressed in normal form are performed by removing an appropriate component from the function. Approximations of clock gating functions expressed in conjunctive normal form are performed by removing a clause from the function. Approximations of clock gating functions expressed in disjunctive normal form are performed by removing a literal from a clause in the function.

The invention discloses a constraint-based system fault injecting method. The method comprises the steps of: classifying constraints into atomic condition and conjunction normal form clause levels according to atomic condition inversion and the conjunction normal form clause inversion strategies and solving a group of negative forms of the specification constraints at the levels to serve as basesof generating fault data; replacing constraint variables in the inverted constraints with normal input combinations, gradually carrying out slack replacement on the constraint variables and finding minimum-variation fault data which have the least number of slack variables and are closest to a real situation through a constraint solving operation; carrying out faulty injection on a to-be-tested system by taking the minimum-variation fault data as test inputs to obtain fault injecting results. The method disclosed by the invention has the beneficial effects that by adopting a new fault injecting technology, the more real and more sufficient fault data are generated; the error detecting capability of the fault injection is strengthened; and faults close to the normal state are also beneficial for a tester to repair and eliminate the defects at the same time.

The invention provides an SAT automatic integrated solver based on FPGA, which effectively judges that whether CNF can be met. Firstly, the CNF is automatically translated to the verilog language by a C++ translator, i.e. the conjunctive normal form is converted to the gate level circuit form; the gate level circuit is simulated via Questasim software, whether the simulation is the same with a theoretical logic is checked, then the circuit is optimized and synthesized via Precision software, at last QuartusII software integrated into the Precision software is called to perform pin configuration, thus the integrated file is finally downloaded onto the FPGA circuit board to be cured into the hardware logic for verification; and the cured FPGA chip is embedded into the embedded chip, the automation of the whole process for generating a file calling command is achieved through combined programming of the Tcl scripting language and high-level language C++, and thereby whether the CNF can be met is rapidly judged. The hardware compiling configuration time is added, and thereby the time of the whole process can be more accurately computed compared with other hardware SAT solvers.