Formation method of semiconductor structure

Abstract

The invention relates to a formation method of a semiconductor structure. The method includes the following steps that: a semiconductor substrate is provided; a mask layer with an opening is formed on the surface of the semiconductor substrate, wherein the opening exposes a part of the surface of the semiconductor substrate; the semiconductor substrate is etched along the opening, so that first through holes can be formed in the semiconductor substrate; oxidation treatment is performed on the surfaces of the side surfaces of the first through holes, so that an oxide layer can be formed, the oxide layer is removed, so that second through holes are formed, the roughness of the side walls of the second through holes is made to be smaller than that of the side walls of the first through holes, or annealing treatment is performed on the side walls of the first through holes, so that second through holes can be formed, and the roughness of the side walls of the second holes is made to be smaller than that of the side walls of the first through holes. With the above method adopted, the roughness of the side walls of the second holes formed in the semiconductor substrate can be decreased.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a method for forming a semiconductor structure. Background technique [0002] With the continuous development of semiconductor technology, the feature size of semiconductor devices has become very small. It is becoming more and more difficult to increase the number of semiconductor devices in a two-dimensional packaging structure. Therefore, three-dimensional packaging has become a method that can effectively improve chip integration. degree method. Current three-dimensional packaging includes gold wire bonding-based chip stacking (DieStacking), package stacking (PackageStacking), and three-dimensional (3D) stacking based on through-silicon vias (ThroughSiliconVia, TSV). Among them, the three-dimensional stacking technology using through-silicon vias has the following three advantages: (1) high-density integration; (2) greatly shortening the length of electrical interconn...

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Problems solved by technology

[0004] However, the sidewall surface of the TSV formed in the prior art is generally rough, resulting in poor quality of the conductive material filled in the TSV, thus affecting the electrical connection performance in the semiconductor device

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