Flash memory and production method thereof

Abstract

The invention discloses a flash memory and a production method thereof. The flash memory comprises a stacked gate structure, a first doped area, a second doped area, a selective gate, and a gate dielectric layer. The stacked gate structure is disposed on a substrate, and the stacked gate structure comprises, from the substrate, sequentially a tunneling dielectric layer, a floating gate, an inter-gate dielectric layer, and a control gate. The first doped area and the second doped area are respectively disposed in the substrate on two sides of the stacked gate structure. The selective gate is disposed in the groove of the substrate under the stacked gate structure, and the selective gate is disposed next to the first doped area, and the distance is arranged between the selective gate and the second doped area. The gate dielectric layer is disposed between the selective gate and the substrate. The tunneling dielectric layer is disposed between the floating gate and the selective gate, and between the floating gate and the substrate.

Description

technical field [0001] The present invention relates to a semiconductor element, and in particular to a flash memory and a manufacturing method thereof. Background technique [0002] Flash memory components have the advantages of being able to store, read, and erase data multiple times, and the stored data will not disappear after power failure, so it has become widely used in personal computers and electronic devices. A non-volatile memory element. [0003] A typical flash memory device uses doped polysilicon to make a floating gate (FloatingGate) and a control gate (ControlGate). Moreover, the floating gate is separated from the control gate by a dielectric layer, and the floating gate is separated from the substrate by a tunnel oxide layer (TunnelOxide). When writing / erasing (Write / Erase) data to the flash memory, by applying a bias voltage to the control gate and the source / drain region, electrons are injected into the floating gate or electrons are released from the f...

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Problems solved by technology

However, the shortening of the gate length will shorten the channel length (ChannelLength) under the tunnel oxide layer, so when programming this memory cell, abnormal electrical penetration (PunchThrough) will easily occur between the drain region and the source region. ), which will seriously affect the electrical performance of the memory cell

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