Clock duty ratio adjusting circuit

Abstract

The invention relates to a clock duty ratio adjusting circuit. The clock duty ratio adjusting circuit comprises a pulse generator, an RS trigger, a duty ratio detector, an adjusting circuit and a D trigger. The pulse generator, the RS trigger and the adjusting circuit are successively connected. The pulse generator is connected to the S input end of the RS trigger; the output end of the RS trigger is connected respectively to the D trigger, the duty ratio detector and the input end of the adjusting circuit; the anti-phase output end of the D trigger is connected to the input end of the duty ratio detector; the output end of the duty ratio detector is connected to the input end of the adjusting circuit; the output end of the adjusting circuit is connected to the R input end of the RS trigger; inputted clock signals are accessed into the pulse generator and the D trigger. According to the invention, an RS trigger is adopted to integrate the edges of a clock. The paths of the duty ratio detector and the adjusting circuit are separate from their output path. The signal outputting path is rather simplified and features low shaking characteristics. The adoption of integrator negative feedback continuous time adjusting enables high accuracy.

Description

technical field [0001] The invention belongs to the technical field of clock circuit design in integrated circuits, and in particular relates to a clock duty ratio adjustment circuit. Background technique [0002] At present, with the continuous development of integrated circuit technology, as the mainstream structure of high-speed and high-precision ADCs, the accuracy and speed that can be realized by pipeline-structured ADC circuits continue to increase. However, the data conversion process of each sub-stage circuit in the pipeline ADC circuit structure inevitably needs to be controlled by two-phase non-overlapping clocks. The stage circuit conversion has sufficient settling time and the highest clock utilization efficiency. The 50% duty cycle clock can not only realize the stable operation of the high-speed pipeline ADC system, but also achieve the best conversion performance. [0003] Because the clock signal is affected by the signal attenuation on the transmission lin...

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Problems solved by technology

[0003] Because the clock signal is affected by the signal attenuation on the transmission line, the mutual interference of other signals, the threshold fluctuation of the inverter transistor caused by the process, and the deviation of the rising and falling edges during the propagation process, the clock circuit of the high-speed pipeline ADC cannot guarantee the stability of the clock signal duty cycle.

In the process of high-frequency signal processing, the accumulative effect of clock misalignment in the transmission link makes the duty cycle misalignment worsen, affecting the normal jumping and flipping of the clock, causing timing disorder, functional error and even failure

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