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Multi-core parallel protocol stack structure design method based on GMR-1 3G system

A technology of structure design and protocol stack, applied in the field of Uu interface protocol stack access layer design, to achieve the effect of reducing processing delay, fast processing speed and strong real-time performance

Inactive Publication Date: 2016-08-03
XIDIAN UNIV
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Problems solved by technology

[0006] With the improvement of people's requirements for signal processors, the development of signal processors with single-core architecture has encountered a bottleneck

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  • Multi-core parallel protocol stack structure design method based on GMR-1 3G system
  • Multi-core parallel protocol stack structure design method based on GMR-1 3G system
  • Multi-core parallel protocol stack structure design method based on GMR-1 3G system

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Embodiment Construction

[0019] The present invention will be further described below in conjunction with accompanying drawing.

[0020] Such as figure 1 The core control module shown: This module is the core of the RRC layer design. It completes the organic management of the entire protocol stack through event monitoring and timer management. It mainly uses the state machine as the center to control the operation of the entire RRC functional entity. RRC function control module: This module mainly completes the interaction between the interface between the RRC module and other modules, and the signaling interaction of all processes is completed through this module. Parameter configuration management module: It mainly completes a series of functions such as GSC's management of multiple cells, system broadcast, registration to the core network, public channel configuration, and cell establishment. Core data structure module: This module contains various information of all connected terminals on the bas...

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Abstract

The invention discloses a multi-core parallel protocol stack structure design method based on a GMR-1 3G system to solve the problem that data transmission is of long delay and low processing speed in the prior art. On the basis of the GMR-1 3G standard, the layers of a protocol stack are reasonably divided into modules, and the modules are distributed through reasonable task distribution to the cores of a multi-core processor for parallel running. An inter-core communication mechanism adopts a Message Q mode which consumes less time and enables variable-length data to be transmitted, and the processing speed is increased effectively. The protocol layers run on different board cards which communicate based on a TCP / IP protocol. The type of a message is judged in the transmission process of the message. If the message is a heartbeat packet for judging whether connection is normal, the message is transmitted in a pass-through way, processing by PDCP and RLC is ignored, and the processing delay is reduced. In order to guarantee the stability of the clock, the clock is individually distributed to one core for running. The method of the invention gives consideration to the system transmission delay, system throughput and other factors.

Description

technical field [0001] The invention belongs to the field of broadband wireless communication protocol stacks, and in particular relates to a design method for a Uu interface protocol stack access layer of a GMR-13G system. Based on the GMR-13G standard, each layer is divided into modules reasonably, and each module is allocated to each core of the multi-core processor to run in parallel through a reasonable task allocation method, thereby reducing the processing delay. The present invention takes into account factors such as system transmission delay and system throughput at the same time. Background technique [0002] Most of the new-generation satellite mobile communication systems support the GMR-13G standard (GMR, GeostationaryearthorbitMobileRadiointerface), which is a geosynchronous satellite mobile communication air interface technology issued by the European Telecommunications Standards Institute (ETSI) that can be interconnected with the terrestrial 3G core network...

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Application Information

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IPC IPC(8): H04L29/06H04W92/04H04W92/10G06F9/50
CPCH04L69/03G06F9/5011H04W92/045H04W92/10
Inventor 安小静
Owner XIDIAN UNIV
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