Logic locking achieving device and method for multi-channel ultrasonic front-end chip

Abstract

The invention discloses a logic locking achieving device and method for a multi-channel ultrasonic front-end chip. The device is arranged in a circuit of a multi-channel ultrasonic device and at least comprises the front-end chip used for ultrasonic simulation and further comprises a programmable logic unit with a logic locking function. Low-voltage differential signal pins of the front-end chip are directly connected with logic locking pins of the programmable logic unit respectively. According to the logic locking achieving device and method for the multi-channel ultrasonic front-end chip, as the mode that the low-voltage differential signal pins of the front-end chip are directly connected with the logic locking pins of the programmable logic unit respectively, the ultrasonic device which can conduct quick compiling and quickly respond to a processing requirement is formed.

Description

technical field [0001] The invention relates to a multi-channel ultrasonic chip circuit and its function improvement, in particular to the improvement of the connection structure between the front-end chip and the FPGA, the drive design, and the logic locking implementation method. Background technique [0002] In the multi-channel ultrasonic device circuit of the prior art, the front-end chip of ultrasonic simulation is usually used, such as the AFE5805 chip of TI (Texas Instruments), which is a low-power and small-sized front-end specially designed for the ultrasonic device system. Chip, designed with eight channels, including low-noise amplifier (LNA, low-noise amplifier), voltage-controlled attenuator (VCA, voltage-controlled attenuator), programmable gain amplifier (PGA, programmable gain amplifier), low-pass filter (LPF, low-pass filter), and a 12bit analog-to-digital converter (ADC, analog-to-digital converter) which has a low-voltage differential signal (LVDS, low vo...

AI Technical Summary

Problems solved by technology

[0006] On the one hand, because the official code does not have an effective verification mechanism in the actual system, it is difficult to debug and verify at the beginning of the design

On the other hand, the logic resources and PLL resources of the FPGA are more occupied, and the compilation result has a greater relationship with the compilation environment and the total resource consumption of the FPGA. It is easy to have deviations in product design, resulting in design errors, and it is not easy to find design deviations and The problem of failure

Third, due to the multi-chip and multi-channel design, the PCB layout of each channel is likely to be different. After the FPGA is powered on, it will always perform "self-learning" processing for each channel, and it will take a long time to enter the "user mode". ", resulting in slow device processing and response, affecting the user experience of use

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