8 results about "Logic locking" patented technology

The invention relates to the technical field of industrial data analysis, and discloses an original data feature analysis system in water meter detection, comprising: a pulse data aggregation unit for acquiring an original pulse time sequence; the time sequence difference processing unit is used for receiving the original pulse time sequence and executing first-order difference operation to generate a first-order time sequence difference value sequence; the feature decoupling shunting unit is used for executing logic locking by using a monitoring carrier environment baseline scalar, and dividing a first-order time sequence difference value sequence into a steady state processing channel and a transient analysis channel; the intrinsic mode mapping unit is used for pre-storing intrinsic mode feature vectors; the transient distortion judgment unit is used for extracting the frequency domain feature vector, executing orthogonal projection mapping with the intrinsic mode feature vector and outputting an effective transient distortion tensor, the problem of feature information entropy collapse of the high-frequency pulse sequential sequence in the dimensionality reduction aggregation process is solved, and a semantic gap between an information processing domain and a physical design domain is eliminated.

The application discloses a distributed operation and maintenance management system of energy storage power station based on Internet of Things, and relates to the technical field of power system automation and safe operation and maintenance. The passive intelligent locking device adopts passive radio frequency coupling power supply design, is internally provided with a radio frequency receiving coil and an energy storage capacitor, obtains electric energy by receiving radio frequency signals emitted by an intelligent computer key, and is internally further provided with a secondary locking mechanism. The secondary locking mechanism comprises a mechanical blade structure and a magnetic pin structure. An operation order expert system based on natural language processing is embedded in an operation and maintenance management cloud platform, is used for analyzing unstructured operation instructions and automatically generating standard operation orders, and simultaneously performs five-prevention logic verification on the operation orders in combination with a logic locking program. The application has the advantages that the secondary locking structure of the mechanical blade and the magnetic pin greatly improves the anti-technology opening time, and in combination with AES-256 encrypted communication, the physical and information dual safety is ensured.

The invention discloses an SAT elastic logic locking module for improving output damage, a module variant and application, and relates to the technical field of hardware security, the SAT elastic logic locking module comprises an n-bit traveling wave carry adder, a controllable output damage unit and a first AND gate; the module variant of the SAT elastic logic locking module is that a comparator and a second AND gate are added on the basis of the SAT elastic logic locking module; an SAT elastic logic locking module or a module variant forms an integrated circuit with an SFLL or an SARLock, and the integrated circuit can be applied to resisting deletion attacks, sensitization attacks, function analysis attacks and AppSAT attacks. According to the method, the effective resistance to the SAT attack is realized, and a new technical enlightenment is provided for the development of an SAT attack resistance technology.

The present application relates to the technical field of signal processing, in particular to a resistor adjusting method and system based on MEMS technology. The present application constructs an initial conduction link by preferentially screening a topology structure with the maximum number of parallel branches, maximizes the current shunt capability at the physical level and provides redundancy space for subsequent adjustment, quantifies the load deviation degree based on the real-time collected branch current distribution data, accurately modulates the electrostatic driving force applied to a specific micro-cantilever beam by using the sensitivity mapping relationship of the driving voltage to the contact resistance, dynamically compensates the impedance difference between the branches by fine-tuning the contact pressure of the contact point, forcibly realizes the uniformization of current distribution to eliminate local hot spots and suppress the electron migration effect, and executes the maximum common substructure matching logic under the resistance value transition instruction, locks the driving voltage state of the coincident node to inherit the established load balancing parameters, and only minimizes the action of the switch combination of the residual part.

The invention discloses a multi-key activation logic locking system and method, and the method achieves the dynamic verification of an activation key sequence and the correction locking of error input through the storage of a function key and N activation keys in a memory, and in combination with the design of a trigger module and a correction circuit of an activation module. When the input activation key logic value is consistent with the trigger state output signal, the correction circuit outputs an effective key to drive the trigger state to transition, and when the input activation key logic value is inconsistent with the trigger state output signal, the trigger state is locked as a correction value, so that the brute force cracking difficulty is remarkably improved. Meanwhile, the blocking logic circuit controls the validity of the functional key and signal transmission through an activation signal. According to the embodiment of the invention, a multi-stage key control mechanism and a single-key model which destroys SAT attack dependence are constructed, high security, low hardware overhead and strong expansibility are integrated, integrated circuits of different scales can be flexibly adapted, and the anti-attack capability of the integrated circuit is fundamentally enhanced.

This application discloses a multi-key activation logic locking system and method. By storing a function key and N activation keys in memory, and combining the trigger module and correction circuit design of the activation module, dynamic verification of the activation key sequence and correction locking of erroneous inputs are achieved. When the input activation key logic value matches the trigger state output signal, the correction circuit outputs a valid key, driving the trigger state transition; otherwise, it locks the corrected value, significantly increasing the difficulty of brute-force attacks. Simultaneously, the blocking logic circuit controls the validity of the function key and signal transmission through the activation signal. The embodiments of this application construct a multi-stage key control mechanism, disrupting the single-key model relied upon by SAT attacks. It combines high security, low hardware overhead, and strong scalability, flexibly adapting to integrated circuits of different scales, fundamentally enhancing the anti-attack capability of integrated circuits.

The application relates to the field of avionics fault diagnosis, and discloses a multi-parameter intelligent diagnosis algorithm for evaluating the quality of an aircraft power supply, which receives loop voltage and current and bus control instruction data in parallel, constructs time-aligned heterogeneous data streams based on a clock, and locks key load action events by using double trigger logic. By calculating equivalent Thevenin source impedance and constructing a background noise model, the adaptive reference waveform is generated by correcting the load standard model. The measured and reference waveforms are aligned by using dynamic time warping, the deformation cost is output, and the energy spectrum entropy is extracted by performing wavelet packet decomposition on the differential residual. The multi-dimensional feature vector is constructed by comprehensively considering impedance drift, deformation cost and energy spectrum entropy, and the mechanical fault, electrical contact degradation and line aging are decoupled by using hierarchical logic. The application effectively eliminates background interference and time jitter, and realizes accurate evaluation of the state of the power supply system.

This invention discloses a logic hardware power-on and power-off monitoring and protection circuit, comprising M levels of hardware protection units. When M is greater than 2, each level of hardware protection unit conforms to a preset design rule. The preset design rule is as follows: when the number of design levels of the hardware protection unit to be designed is ≥2 and <M, an AND logic relationship is formed between the power undervoltage alarm monitoring signals of all preceding hardware protection units and the overall system fault monitoring signal to output the intermediate output signal of the hardware protection unit to be designed. Conversely, an OR logic relationship is formed between the intermediate output signal of the hardware protection unit to be designed and the overall system fault monitoring signal to output the output signal of the hardware protection unit to be designed. This invention uses a fully hardware logic circuit and a clever and rigorous logic link to achieve logic locking under power-on and power-off conditions, resulting in low cost, high reliability, and easy expansion.