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Method for preparing silicon-based nano-pattern array structure

A nano-pattern and array structure technology, applied in nanotechnology, semiconductor/solid-state device manufacturing, electrical components, etc., can solve the problems of increasing manufacturing cost and strict process requirements, and achieve the effect of reducing manufacturing cost and simplifying operation steps.

Active Publication Date: 2020-02-04
SUZHOU INST OF NANO TECH & NANO BIONICS CHINESE ACEDEMY OF SCI
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, since photolithography or nanoimprinting methods are required to prepare patterned substrates of this size, this increases the production cost and requires strict processes.

Method used

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  • Method for preparing silicon-based nano-pattern array structure
  • Method for preparing silicon-based nano-pattern array structure
  • Method for preparing silicon-based nano-pattern array structure

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Embodiment Construction

[0014] The invention provides a method for preparing a silicon-based nano-pattern array structure. The method prepares a mask through two anodic oxidations, thereby fundamentally reducing the production cost. In addition, because the electrochemical method of anodic oxidation is simpler and easier than the methods of nanoimprinting and gluing, it can greatly meet the production needs.

[0015] Exemplary embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings, however, the accompanying drawings only schematically illustrate specific examples of the present invention and are not limiting. However, it should be understood by those skilled in the art that various modifications and variations can be made thereto without departing from the scope of protection defined by the claims of the present invention.

[0016] Figure 1 to Figure 4 Sequentially schematically shows a cross-sectional schematic view of the process of pre...

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Abstract

The invention provides a method for preparing a silicon-based nano-pattern array structure, the method comprising: setting a silicon substrate; depositing a barrier layer on the silicon substrate, and depositing an aluminum film on the barrier layer; The film is anodized once to form a first nano-pattern array structure on the surface of the aluminum film away from the silicon substrate; the second acid solution is used to remove the first nano-pattern array structure; the third acid solution is used to treat the aluminum film Perform secondary anodizing to form the aluminum film into an aluminum oxide nano-pattern array structure; use the aluminum oxide nano-pattern array structure as a mask to etch the barrier layer and the silicon substrate to form the silicon substrate and the barrier layer into a It has a nano-pattern array structure corresponding to the aluminum oxide nano-pattern array structure; the aluminum oxide nano-pattern array structure on the silicon substrate and the barrier layer formed as the nano-pattern array structure are removed by using a buffered oxide etchant, thereby obtaining a silicon substrate Nano pattern array structure.

Description

technical field [0001] The invention relates to a method for preparing a patterned substrate, in particular, the invention relates to a method for preparing a silicon-based nanometer pattern array structure. Background technique [0002] As silicon-based semiconductor devices shrink in size, traditional bulk silicon materials are approaching their physical limits. Germanium and Ⅲ-Ⅴ main group materials have attracted widespread attention due to their superior performance compared with silicon materials in applications. However, germanium and III-V main group materials are expensive, and they are not compatible with silicon-based processes. In addition, when silicon-based epitaxy, germanium and III-V main group materials cannot form a good lattice match with silicon, resulting in high dislocation defects. In order to solve the above problems, a series of patterned substrate technologies have been proposed and developed, especially GaAs epitaxy requires the size of the patte...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/02B82Y40/00
Inventor 赵迎春熊敏董旭
Owner SUZHOU INST OF NANO TECH & NANO BIONICS CHINESE ACEDEMY OF SCI