Double-layer wear-leveling method and system

A wear leveling, two-layer technology, applied in memory systems, memory address/allocation/relocation, instruments, etc., can solve problems such as ineffective defense against malicious attack programs

Active Publication Date: 2016-09-21
HUAZHONG UNIV OF SCI & TECH
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, the existing wear leveling algorithm cann

Method used

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  • Double-layer wear-leveling method and system
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  • Double-layer wear-leveling method and system

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Embodiment Construction

[0083] In order to facilitate understanding of the present invention, at first the following nouns appearing in the present invention are explained:

[0084] Physical row: The most basic access unit of the memory system. On different systems, the row size can be different. Usually a row size can be 64 bytes, 128 bytes, 256 bytes;

[0085] Region: A storage area in the memory space, consisting of several physical rows. Usually a region can consist of 2048, 4096 and 8192 rows;

[0086]Logical row address: the address requested by the upper layer application, which is a virtual address, recorded as LA

[0087] Middle row address: the address corresponding to the logical address after being mapped by the upper layer, which is a virtual address and is denoted as IA.

[0088] Physical row address: the address corresponding to the physical device, it is a real address, recorded as PA;

[0089] Remapping: Change the correspondence between logical row addresses and physical row ad...

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Abstract

The invention discloses a double-layer wear-leveling method and system, and is suitable for the memory of a phase transition storage. The method specifically comprises the following steps: an outer layer is in charge of mapping the storage area logic address of the whole memory to a middle address, and a secrete key is exchanged before a malicious program detects the integral secret key through the increase of the complexity of the secret key; and an inner layer is in charge of using an independent algebra wear-leveling method in each subarea to realize wear-leveling in the area under a situation of low expenditure. The problem that the safety of a memory system is lowered since the secret key of the wear-leveling algorithm is leaked since the phase transition storage has the time delay difference of a resetting operation and a setting operation can be solved.

Description

technical field [0001] The invention belongs to the field of solid-state storage, and in particular relates to a double-layer wear leveling method and system, which are suitable for phase-change memory. Background technique [0002] With the development of multi-core technology, computer systems have higher and higher requirements for memory. However, due to the constraints of scalability and leakage power consumption, traditional dynamic random access memory (DRAM) memory cannot meet the application requirements of new environments, and its development is limited. Phase Change Memory (PCM) has the advantages of high scalability, large capacity, low power consumption and high performance, and is the most competitive candidate to replace DRAM as the next generation memory. [0003] However, the biggest challenge faced by PCM is the endurance limit, that is, each storage unit can only withstand 10 7 -10 8 time to write. In the case of uniform distribution of write requests...

Claims

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Application Information

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IPC IPC(8): G06F12/02G06F21/79
CPCG06F12/0246G06F21/79
Inventor 冯丹黄方亭夏文周文鄢磊张宇成付忞周玉坤
Owner HUAZHONG UNIV OF SCI & TECH
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