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Reconfigurable DBF algorithm hardware accelerator and control method

A hardware accelerator and algorithm technology, applied in the direction of instrumentation, electrical digital data processing, etc., can solve problems such as limited throughput, failure to meet real-time requirements for fast processing, and failure to solve core problems

Active Publication Date: 2016-09-21
NANJING UNIV
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Problems solved by technology

For many fields such as radar imaging with high real-time requirements, using a common solution—that is, using DSP for signal calculations, will be greatly limited by the throughput rate, and it is far from meeting the real-time requirements of fast processing.
However, relying solely on increasing the main frequency of the processing components and the communication bandwidth of the storage components cannot solve the core problem, and the design architecture is the bottleneck.

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  • Reconfigurable DBF algorithm hardware accelerator and control method
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  • Reconfigurable DBF algorithm hardware accelerator and control method

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Embodiment Construction

[0036] The scheme of the present invention will be described in detail below in conjunction with the accompanying drawings. In this embodiment, the Xilinx VC707 FPGA development board is used as the implementation platform.

[0037] like figure 1 , the reconfigurable DBF algorithm hardware accelerator in this embodiment includes a GMAC interface, a reconfiguration control module, a data storage module, and a DBF operation module. Among them, the GMAC interface is used to realize the data transfer between the reconstruction control module in the DBF algorithm accelerator and the host computer. The reconstruction control module is connected with the GMAC interface, the data storage module and the DBF operation module, and is used to reconstruct the parameters of the DBF algorithm, the number of parallel paths and the storage structure. The data storage module is connected with the DBF operation module and is used for writing, storing and reading data. The DBF operation module ...

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Abstract

The invention relates to a reconfigurable DBF algorithm hardware accelerator and a control method. The accelerator comprises a reconfiguration control module which is used for receiving DBF algorithm information data sent out by an upper computer, and deciding whether to send out a reconfiguration control signal according to DBF algorithm information; a data storage module which is used for finishing writing, storage and reading of the DBF algorithm information data; and a DBF operation module which is used for reading data from the data storage module, finishing operation of a DBF algorithm and outputting a corresponding result. The reconfigurable DBF algorithm hardware accelerator and the control method provided by the invention have the following beneficial effects: the contradictions that a special DBF processor is poor in universality and the speed of calculating the DBF by a universal processor is slow can be solved, and a reconfigurable architecture can improve the flexibility of the algorithm, realize full pipeline output of source data, and improve the operation efficiency and timeliness of the algorithm.

Description

technical field [0001] The invention relates to a DBF algorithm processing unit based on fixed resources and its hardware implementation, in particular to a reconfigurable DBF algorithm hardware architecture. Background technique [0002] Digital signal processing technology is not only widely used in multimedia, data communication, radar imaging, geological exploration, aerospace and other engineering technology fields, but also has become one of the theoretical foundations of emerging disciplines such as artificial intelligence, pattern recognition, and neural networks in recent years. widely. With the continuous improvement of semiconductor technology and the rapid development of DSP devices, it is possible to process large quantities of data in real time. However, for many fields such as radar imaging with high real-time requirements, the general solution—that is, to use DSP for signal calculation, will be greatly limited by the throughput rate, which is far from meetin...

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F13/16G06F13/40
CPCG06F13/1668G06F13/4068
Inventor 潘红兵李晨杰吕飞秦子迪陈金锐李丽李伟
Owner NANJING UNIV