Reconfigurable DBF algorithm hardware accelerator and control method
A hardware accelerator and algorithm technology, applied in the direction of instrumentation, electrical digital data processing, etc., can solve problems such as limited throughput, failure to meet real-time requirements for fast processing, and failure to solve core problems
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[0036] The scheme of the present invention will be described in detail below in conjunction with the accompanying drawings. In this embodiment, the Xilinx VC707 FPGA development board is used as the implementation platform.
[0037] like figure 1 , the reconfigurable DBF algorithm hardware accelerator in this embodiment includes a GMAC interface, a reconfiguration control module, a data storage module, and a DBF operation module. Among them, the GMAC interface is used to realize the data transfer between the reconstruction control module in the DBF algorithm accelerator and the host computer. The reconstruction control module is connected with the GMAC interface, the data storage module and the DBF operation module, and is used to reconstruct the parameters of the DBF algorithm, the number of parallel paths and the storage structure. The data storage module is connected with the DBF operation module and is used for writing, storing and reading data. The DBF operation module ...
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