Clock Tree Routing Method Based on SAT Algorithm

Abstract

The embodiment of the invention discloses a clock tree routing method based on an SAT algorithm. The method comprises following steps: obtaining clock wires, reset wires and enabling wires, saving clock wires, reset wires and constraints of enabling wires from user's design; obtaining a first clock network map from a chip model, saving nodes of the first clock network map and multi-path selector constraints included in the first clock network map, and configuring constraints between multi-path selectors and constraints of multi-path selector connection relations; generating clauses in the WEF format according to the clock wires, reset wires and constraints of enabling wires and constraints included in the first clock network map; calling the satisfiable SAT algorithm for clauses in order to obtain at least one solutions meeting constraints; and labeling any mathematical solution tag corresponding to any solution of at least one solution to the clock wires, reset wires and enabling wires such that routing of a clock tree is finished.

Description

technical field [0001] The invention relates to the technical field of integrated circuit design in the field of microelectronics, in particular to a clock tree wiring method based on a SAT algorithm. Background technique [0002] Field Programmable Gate Array (Field Programmable Gate Array, "FPGA" for short), is a logic device with abundant hardware resources, powerful parallel processing capability and flexible reconfigurable capability. Therefore, FPGA is more and more widely used in data processing, communication, network and other fields. [0003] The FPGA design process includes: design entry, debugging, functional simulation, synthesis, layout and routing, timing simulation, configuration download and other steps. Among them, the layout refers to the reasonable adaptation of the hardware primitives or underlying units in the logic netlist to the inherent hardware structure inside the FPGA. The quality of the layout has a great impact on the final result of the design...

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Problems solved by technology

[0004] However, the existing FPGA clock tree routing method uses a general routing algorithm, it is difficult to consider and plan the clock tree from a global perspective, so it is impossible to get all the routing methods that satisfy the constraints

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