Power reduction in thyristor random access memory

Abstract

A volatile memory array using vertical thyristors is disclosed together with methods of reducing power consumption in such arrays.

Description

[0001] Cross References to Related Applications [0002] This patent application is related to U.S. Patent Application No. 14 / 841140, entitled "Thyristor Volatile Random Access Memory and Methods of Manufacture", filed on the same date, and entitled "Methods of Reading and Writing Data in a Thyristor Random Access Memory" filed on the same date U.S. Patent Application No. 14 / 841521, filed on the same date, U.S. Patent Application No. 14 / 841578 entitled "Methods of Retaining and Refreshing Data in a Thyristor Random Access Memory"; Priority to U.S. Provisional Patent Application No. 62 / 186336, filed on 29th, entitled "High-Density VolatileRAMs, Method of Operation and Manufacture Thereof," and is entitled "Cross-Coupled Thyristor Continuation-in-Part of U.S. Application No. 14 / 590834 for SRAM Circuits and Methods of Operation, which claims priority to U.S. Provisional Patent Application No. 62 / 055582, filed September 25, 2014; incorporated by reference for all purposes All appli...

AI Technical Summary

Problems solved by technology

Unfortunately, the use of epitaxial or CVD semiconductor layers at the back end of standard CMOS processes adds thermal cycling and etching steps, which can degrade the performance and yield of other devices formed earlier on the same substrate

Additionally, PNPN devices operating in the breakdown regime present challenges in terms of process control and power consumption

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